THESIS
2018
xxi, 179 pages : illustrations ; 30 cm
Abstract
GaN-based power devices are becoming promising candidates for power electronic applications, which benefits from the superior material properties of GaN compared with those of Si. A Si-GaN cascode configuration is widely adopted for practical use of GaN-based devices in power switching applications. However, this two-chip co-package approach introduces large interconnection parasitics (especially the parasitic inductance) during assembly. These large parasitics will cause undesirable ringing during fast switching, resulting in system instability and increased switching losses. One efficient way of minimizing parasitics is to monolithically integrate the Si and GaN-based devices on the same substrate with small interconnection distance. In doing so, the chip size and assembly costs can a...[
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GaN-based power devices are becoming promising candidates for power electronic applications, which benefits from the superior material properties of GaN compared with those of Si. A Si-GaN cascode configuration is widely adopted for practical use of GaN-based devices in power switching applications. However, this two-chip co-package approach introduces large interconnection parasitics (especially the parasitic inductance) during assembly. These large parasitics will cause undesirable ringing during fast switching, resulting in system instability and increased switching losses. One efficient way of minimizing parasitics is to monolithically integrate the Si and GaN-based devices on the same substrate with small interconnection distance. In doing so, the chip size and assembly costs can also be reduced.
First, the process compatibilities, especially the influence of high-temperature treatment on AlGaN/GaN epitaxial layers, are evaluated. The process module of growing AlGaN/GaN epitaxial structure in the recessed windows on the Si (111) substrate by selective epitaxial growth (SEG) is developed. In doing so, a planar arrangement of Si and GaN device surface can be achieved for the subsequential device fabrication.
Second, a Si-GaN cascoded diode is experimentally demonstrated by using the proposed monolithic integration technology. It features a differential specific on-resistance (R
sp) of 2.8 mΩ∙cm
2, and a breakdown voltage (V
BD) of 557 V with a small reverse leakage current. Furthermore, the reverse recovery charge (Q
rr) of the cascoded diode is 79% less than that of Si fast recovery diode (FRD). The switching characteristics of the fabricated cascoded diode also demonstrate the much less parasitic effects compared with the wire-bonded counterpart.
Third, a Si-GaN cascoded field effect transistor is designed and experimentally demonstrated. The Si and GaN transistors are placed in a distance of 50 μm which is only 2.5% of that of the conventional two-chip co-package approach (~ 2 mm). The fabricated cascoded FET features normally-off functionalities with a threshold voltage of 3.2 V, a drive current of 1850 A/cm
2 (630 mA/mm) at the gate bias of 15 V, a gate swing of 20 V, a specific on-resistance of 3.3 mΩ∙cm
2 and a breakdown voltage of 696 V. It is shown that the Si-GaN monolithic cascoded FET is promising for a lot of high performance power switching applications
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