High-speed high-precision analog-to-digital converters (ADCs) are widely used in the fields of image processing, information storage and wireless communication. To achieve high speed and high precision, relative to other structures, a pipeline-architecture ADC has an advantage: it can take both accuracy and speed into account. With the continuous improvement of integrated circuits (IC) manufacture process, the speed limit of the circuit is getting higher and higher. At the same time, however, the process dimension is getting smaller and smaller, with the supply voltage becoming ever lower, which makes it hard for the operational amplifier (op-amp) to achieve high gain. What’s more, the power consumption is usually high because there are many stages in a pipelined ADC, and a powe...[ Read more ]

High-speed high-precision analog-to-digital converters (ADCs) are widely used in the fields of image processing, information storage and wireless communication. To achieve high speed and high precision, relative to other structures, a pipeline-architecture ADC has an advantage: it can take both accuracy and speed into account. With the continuous improvement of integrated circuits (IC) manufacture process, the speed limit of the circuit is getting higher and higher. At the same time, however, the process dimension is getting smaller and smaller, with the supply voltage becoming ever lower, which makes it hard for the operational amplifier (op-amp) to achieve high gain. What’s more, the power consumption is usually high because there are many stages in a pipelined ADC, and a power hungry op-amp is needed in each stage. So pipelined-successive-approximation-register (SAR) ADCs have been introduced to solve this problem.

Using an SAR ADC as the sub-ADC in a pipelined ADC instead of a flash ADC can significantly reduce the system complexity. Usually only two stages and one op-amp are needed for a pipelined-SAR ADC, which gives this architecture a high power efficiency. But the sampling speed is limited as an SAR ADC takes much more time to do the quantization than a flash ADC. So the settling time for a multiplying-digital-to-analog-converter (MDAC) is even less. Another issue is that the higher the first-stage resolution is, the larger the gain bandwidth (GBW) requirement is. So for a 5- or 6-bit first stage, it is not easy to design a high-speed closed-loop MDAC to meet the requirement.

In this work, a pipelined-SAR is designed with an open-loop MDAC. To achieve high speed, an open-loop low-gain and high-bandwidth op-amp is used in the MDAC, and the power-hungry high-gain high-bandwidth amplifier is cancelled to save power. The gain is calibrated in the foreground using a parasitic capacitor array at the MDAC input. To push the sampling speed even higher, separate digital-to-analog-converter (DAC) arrays are used for the MDAC and sub-ADC to reduce the first-stage SAR ADC bit-cycling time constant in order to compress the quantization time. A loop-unrolled asynchronous SAR ADC is used to speed up the sub-ADC further. This architecture uses n comparators for an n-bit ADC. The outputs of the comparators can be directly given to the SAR DAC array without any extra logic and there is also no need for the comparators to do the reset within one conversion period. In this way the SAR logic delay is cancelled. But for this multiple comparators design, the comparator offsets need calibration. The offsets’ values will vary with the input common-mode voltage, so background calibration is used to calibrate the offsets at the corresponding common-mode voltage.

Next, a 12-bit 400-MS/s single-channel pipelined-SAR ADC is implemented using a UMC 65-nm CMOS process with 1.3-V supply voltage. The chip includes a reference buffer, low jitter clock receiver and low-voltage differential signaling (LVDS) output driver. Large decoupling capacitors are used in the ADC chip. The total area of the chip including the pads is 1.875x1.875 mm² with a core area of 0.5 mm x 1.1 mm. The measurement results show that the ADC core consumes 12.5 mW power (the reference buffer, clock buffer and LVDS output driving power are not included). The testing speed is limited to 300 MS/s due to the equipment restriction (logic analyzer). So the power supply is reduced to 1.2-V during testing. After the foreground gain calibration, the signal-to-noise and distortion ratio (SNDR) is 63.55 dB and the spurious free dynamic range (SFDR) is 79.15dB for 10-MHz input. The design achieves a figure of merit (FoM) of 34 fJ/conv-step.