Smart and low-power CMOS image sensor (CIS) has seen an increased attention over the last decade, specially targeting wireless sensor network applications. To further push the power limit, mixed-signal image processing has been embedded within CIS to reduce efforts on signal quantization, data movement and processing. In this thesis, four types of smart CISs with embedded mixed-signal image processing are presented, with focus on image compression, spatial and temporal feature extraction, and a combination of these functions, respectively. The aim is to build a smart image sensor featuring low power with high energy efficiency, improved processing capability and accuracy as well as low area overhead.

The first CIS employs a planned-sensor-distortion (PSD) algorithm to compress i...[ Read more ]

Smart and low-power CMOS image sensor (CIS) has seen an increased attention over the last decade, specially targeting wireless sensor network applications. To further push the power limit, mixed-signal image processing has been embedded within CIS to reduce efforts on signal quantization, data movement and processing. In this thesis, four types of smart CISs with embedded mixed-signal image processing are presented, with focus on image compression, spatial and temporal feature extraction, and a combination of these functions, respectively. The aim is to build a smart image sensor featuring low power with high energy efficiency, improved processing capability and accuracy as well as low area overhead.

The first CIS employs a planned-sensor-distortion (PSD) algorithm to compress image data before transmission or storage. 3-bit PSD imaging is enabled by a column-parallel microshift-guided SAR ADC based on a 3x3 predefined pattern. The data bandwidth is further compressed by a customized lossless encoder using predictive coding and run length coding. High reconstruction image quality with low data rate and low power consumption has been successfully demonstrated by the prototype chip.

The second CIS focuses on local binary pattern (LBP) extraction and edge detection for object analysis applications. A 4-pixel group computation (GC) scheme is developed to efficiently extract 8-direction LBP and edge information. High-speed and energy-efficient column-parallel GC is realized through an innovative group-switchable multi-input-multi-output (MIMO) comparator. The proposed reconfigurable mixed-signal processing circuits have been successfully demonstrated featuring accurate feature extraction with state-of-the-art energy efficiency.

The third proposed CIS embeds motion sensing for event-triggered applications. The sensor is reconfigurable for motion sensing, object segmentation and snapshot. High-frame-rate frame differencing (FD) and low-frame-rate background subtraction (BS) are combined as a cooperative sensing scheme to improve motion detection performance with minimum power overhead. Object segmentation is realized through BS-based region-of-interest imaging, which efficiently reduces both imaging and object localization efforts. Snapshot is performed through full-resolution imaging. Both high area and energy efficiencies have been validated by the prototype multi-mode CIS.

Last but not least, a fourth CIS is demonstrated combining motion sensing, feature extraction and image compression as a System-on-Chip (SoC). This versatile CIS design provides scene-adaptive sensing with optimized power and bandwidth utilization. The proposed design has successfully combined the versatile smart functionalities from above designs with high energy efficiency and compact area, making the prospect of deploying such a sensor for a wide range of wireless camera network applications a reality.