Metal-oxide (MO) semiconductors are expected to be one of the most promising candidates as thin-film transistor (TFT) channels. With the advancement of next-generation flat panel display technologies, technical standards of MO TFTs in active-matrix display backplanes are becoming increasingly higher. This thesis focuses on material modification and device processing to further improve the performance of MO TFTs.

Initially, a new type of hybrid-phase ITZO (hp-ITZO) thin films is proposed as TFT channels by modifying not only the element composition but also the crystal morphology. The thin films own a boosted electron Hall mobility of 30 cm²/Vs, which is verified to surpass both the measured result and calculated upper mobility limit of their counterparts in the amorphous phase. Additio...[ Read more ]

Metal-oxide (MO) semiconductors are expected to be one of the most promising candidates as thin-film transistor (TFT) channels. With the advancement of next-generation flat panel display technologies, technical standards of MO TFTs in active-matrix display backplanes are becoming increasingly higher. This thesis focuses on material modification and device processing to further improve the performance of MO TFTs.

Initially, a new type of hybrid-phase ITZO (hp-ITZO) thin films is proposed as TFT channels by modifying not only the element composition but also the crystal morphology. The thin films own a boosted electron Hall mobility of >30 cm²/Vs, which is verified to surpass both the measured result and calculated upper mobility limit of their counterparts in the amorphous phase. Additionally, they also exhibit many other merits such as suppressed sub-gap states, smooth surface, wide band gap, etc. These are prerequisites to achieve high-performance and reliable MO TFTs.

Next, the feasibility as TFT channels is further confirmed by examining TFTs with a bottom-gate top-contact (BG-TC) architecture. By tuning the oxygen partial pressure and direct-current power during co-sputtering, optimal deposition conditions for the channels with reasonable electrical properties are obtained. The devices without passivation can exhibit high electrical performance, excellent spatial uniformity and long shelf-life. Even though their source/drain (S/D) electrodes are then patterned using a wet etch instead of a lift-off technique to fulfill industrial requirements, the resulted back-channel-etched (BCE) TFTs can still be fabricated successfully via extra over-etch ratio control and prior thermal annealing treatment.

Afterwards, related top-gate TFTs are implemented as building blocks for practical applications. To deposit high-quality gate insulators (GIs), we develop a type of SiO₂ stacks containing a silane-sourced PECVD SiO₂ (SiH₄-SiO₂) layer with a tetraethyl-orthosilicate-sourced PECVD SiO₂ (TEOS-SiO₂) layer underneath. The stacks exhibit strengthened electrical quality compared with their single-layer counterparts, and fabricated top-gate bottom-contact (TG-BC) TFTs are shown to be free of hysteresis with lower off-state current and steeper subthreshold swing thanks to GI engineering. To operate high-mobility MO TFTs in enhancement mode, gate electrode (GE) engineering is introduced by replacing metallic aluminum GEs with conductive indium-tin oxide GEs. Together with the work function, GE permeability for hydrogen diffusion out of and oxygen diffusion into MO channels during post-annealing is also involved to modulate the threshold voltage of devices without degradation. Moreover, by delicately employing two different PECVD SiO₂ layers together with differentiated oxygen annealing strategies, we can further realize top-gate self-aligned (TG-SA) TFTs with good electrical characteristics as well as robust stability against gate-bias stress and thermal processing. This relies on a unique property of the hp-ITZO thin films. The S/D regions capped by the SiH₄-SiO₂ can maintain a low-resistivity state after a long-duration oxygen annealing, whereas the channel regions capped by the TEOS-SiO₂ will return to a high-resistivity state. Thus, it can save not only one photolithography step for S/D electrode patterning but also extra processes for conductive S/D region formation, leading to more cost-effective manufacturing.

Finally, a 2.2-inch monochromatic active-matrix organic-light-emitting-diode display panel using the hp-ITZO TFT technology is demonstrated from layout design, through backplane processing, to system testing. In addition, some of integrated circuits for fully transparent electronics are also implemented with preliminary but promising results.