On-chip power regulation systems are becoming a popular way to supply power to modern processors, digital circuits and SoCs. With the development and improvement in the past two decades, digital LDO could be a potential solution to implement the on-chip power regulation systems. However, digital LDOs suffers from intrinsic ripples due to limit cycle oscillation. Analog-assisted digital LDO (AADLDO) architecture is proposed to solve this problem and can be used as a basic framework to implement the on-chip power regulation systems. The on-chip power regulation systems investigated in this work aims to solve the two urgent existing problems from industry: IR-drop issue in power supply rail and area limitation of on-chip regulators. Meanwhile, fast transient response speed and low quiescen...[ Read more ]

On-chip power regulation systems are becoming a popular way to supply power to modern processors, digital circuits and SoCs. With the development and improvement in the past two decades, digital LDO could be a potential solution to implement the on-chip power regulation systems. However, digital LDOs suffers from intrinsic ripples due to limit cycle oscillation. Analog-assisted digital LDO (AADLDO) architecture is proposed to solve this problem and can be used as a basic framework to implement the on-chip power regulation systems. The on-chip power regulation systems investigated in this work aims to solve the two urgent existing problems from industry: IR-drop issue in power supply rail and area limitation of on-chip regulators. Meanwhile, fast transient response speed and low quiescent current are always critical requirements for on-chip power regulation systems.

First, an on-chip distributed power delivery grid (DPDG) with cooperative regulation and IR-drop reduction based on analog-assisted digital LDOs is proposed, which inherit the merits of low output ripple and sub-LSB current supply ability from the analog control, and the advantage of low supply voltage operation and adaptive fast response from the digital control. With the distributed power delivery topology, the IR-drop across the power supply rail can be reduced, especially in large area power-supply applications. The AADLDOs in the power delivery grid work cooperatively to obtain a balance between improved response speed and power consumption. A prototype of a 3×3 power grid with 9 AADLDOs, providing a total of 500-mA maximum load current with an on-chip 0.9-nF output capacitor, is fabricated in a 65-nm CMOS process to demonstrate the proposed DPDG concept and the effectiveness of this scheme. A maximum voltage undershoot of 125mV is measured with a 450mA/20ns load step, resulting a figure-of-merit as low as 0.28ps.

Second, a single-controller-four-output analog-assisted digital LDO is proposed, which can regulate four output voltage domains with only one digital controller by using an adaptive-time-multiplexing control scheme. The area of the digital controller is 62% smaller compared to the sum of the digital controller area of four independent LDOs. An analog-assisted (AA) loop and a push-pull auxiliary (PPA) loop are used to take over the control in steady state to save quiescent power, reduce output ripple and enhance the response speed. A prototype is fabricated in a 65nm CMOS process. An undershoot voltage of 100mV is measured with a 47mA/20ns load step, resulting a figure-of-merit as low as 0.12ps.