THESIS
2020
x, 164 pages : illustrations ; 30 cm
Abstract
Frequency synthesizer is an essential building block of RF and mm-wave transceivers and dissipates significant portion of power in various wireless communication systems, including Internet-of-Things and high-speed RF and mm-wave
WLAN. In this dissertation, several design techniques are proposed to improve the power
efficiency of frequency synthesizers and deal with distinctive design issues in the emerging wireless applications.
First, to mitigate the phase pulling issue, a low-power phase-tracking receiver (PTRX) is proposed featuring a sub-harmonic mixer with a local oscillator (LO) operating at half of the carrier frequency. A co-design methodology together with current reuse technique is adopted to improve the power efficiency. Fabricated in a 65nm CMOS process, the PTRX prototy...[
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Frequency synthesizer is an essential building block of RF and mm-wave transceivers and dissipates significant portion of power in various wireless communication systems, including Internet-of-Things and high-speed RF and mm-wave
WLAN. In this dissertation, several design techniques are proposed to improve the power
efficiency of frequency synthesizers and deal with distinctive design issues in the emerging wireless applications.
First, to mitigate the phase pulling issue, a low-power phase-tracking receiver (PTRX) is proposed featuring a sub-harmonic mixer with a local oscillator (LO) operating at half of the carrier frequency. A co-design methodology together with current reuse technique is adopted to improve the power efficiency. Fabricated in a 65nm CMOS process, the PTRX prototype measures noise figure of 7.1dB and sensitivity of -88dBm
with 1-Mb/s Bluetooth-Low-Energy (BLE) data while consuming 750μW at 0.4/0.6V supply voltages.
Second, a noise-shifting coupling network is proposed for nonlinear passively-coupled
quadrature voltage-controlled oscillators (QVCOs). The noise contribution by the coupling network is minimized by re-aligning the phases of the noise modulation function and the impulse sensitivity function with a reduced magnitude. In addition, the QVCO with the proposed coupling network also incorporates the transformer-feedback technique to improve its performance in terms of phase noise, quadrature phase error, and low supply voltage. The QVCO prototype operating at 7.9-GHz measures phase noise at 10-MHz offset frequency of -143 dBc/Hz and minimum quadrature phase error of 0.23°
while consuming 27.2 mW with a 0.8-V supply voltage.
Third, a 60-GHz sub-sampling PLL (SSPLL) employs a differential tuning loop to
suppress the reference spur. The VCO frequency is differentially tuned only by NMOS
transistors. An injection-locked frequency divider with a 4
th-order resonant tank is
employed between the VCO and the phase detector to further minimize the spur even without an isolation buffer. The prototyped differential SSPLL measures RMS jitter of
236 fs and reference spur from -43 to -52-dBc over a frequency tuning range from 55.5
to 62 GHz while consuming 23mW from 1.2-V supply corresponding to FoM
jitter of -238.9dB.
Finally, a 60-GHz frequency synthesizer with an implicit phase noise cancelling is
proposed. The phase shifter embedded in a 60-GHz injection locked frequency multiplier is utilized for phase noise cancelling. No extra power-hungry high frequency blocks for phase noise cancelling is required, and the isolation buffer in SSPLL is removed to further improve the power efficiency. Fabricated in a 65nm CMOS process, the frequency
synthesizer prototype measures a 196.4-fs RMS jitter while consuming 13-mW from 1-V supply corresponding to FoM
jitter of -243dB.
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