THESIS
2020
xii, 82 pages : illustrations ; 30 cm
Abstract
As performance improvement from continuous technology scaling of single-core greatly
diminishes, multi-core processors have gained significant popularity. Multi-core processors
are widely used across many application domains, including general-purpose,
embedded, and graphics (GPU). However, multi-core platforms bring tremendous performance
gain as well as incurring severe problems. As the energy consumption of
modern multi-core systems increases every year, power and energy management have
become critical challenges. Higher power consumption transforms into more thermal
dissipation and integrating multiple cores on a single chip makes it much more difficult
to manage thermally than lower-density single-core designs. And also, two and
more processing cores sharing the same memo...[
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As performance improvement from continuous technology scaling of single-core greatly
diminishes, multi-core processors have gained significant popularity. Multi-core processors
are widely used across many application domains, including general-purpose,
embedded, and graphics (GPU). However, multi-core platforms bring tremendous performance
gain as well as incurring severe problems. As the energy consumption of
modern multi-core systems increases every year, power and energy management have
become critical challenges. Higher power consumption transforms into more thermal
dissipation and integrating multiple cores on a single chip makes it much more difficult
to manage thermally than lower-density single-core designs. And also, two and
more processing cores sharing the same memory subsystem limits the real-world performance
advantage. To overcome the above challenges faced by multi-core platforms, in
this thesis, we proposed several novel approaches to optimize the energy consumption,
thermal management, and performance bottleneck for three kinds of popular multi-core
platforms ( 2D modern multi-core, 3D multi-core, and GPUs), through exploiting application
characteristics.
For modern multi-core platforms, the increasing power and energy consumption have
become a critical concern. Studies have shown that dynamic voltage and frequency scaling (DVFS) is an effective approach in reducing the power or energy consumption
of multi-core platforms. However, previous methods that focused on the energy minimization
of the processor cores have overlooked the energy overhead of the off-chip
voltage regulator (VR) which has recently shown to be a non-trivial part of the total
energy consumption. To address this concern, we propose an overall energy optimization
method for the system that minimizes both cores’ energy consumption and VR
energy consumption using DVFS and VR phase scaling by solving a comprehensive
convex model. The power and energy challenges become more salient for the promising
three-dimensional (3D) multi-core architecture,. The multiple vertically stacked
active silicon layers will easily transform the power consumption into hotspot, imposing
reliability threat and device aging. Thus, it is more critical to control the peak
temperature for 3D CMP than 2D multi-core platforms. To address this challenge, we
propose a two-stage thermal-aware task scheduling policy which exploits the application
and system architecture characteristics to decouple the mapping of task-graphs for
the performance and peak temperature optimization into two stages. Another ubiquitous
multi-core architecture, graphics processing units (GPUs), can bring tremendous performance
improvement through integrating hundreds of cores on a single chip. However,
its potential performance speedup is usually limited by the memory subsystem, especially
the small L1 data cache. To overcome the performance bottleneck for GPUs, we
propose an effective array-level cache bypassing method to improve the performance
for general-purpose GPU applications while maintaining the ease of programmability.
Additionally, we try to optimize the energy consumption of GPUs through DVFS.
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