Due to the high reliability, low cost and high availability, silicon-based MOSFETs are widely used for power management integrated circuits (PMICs). Nevertheless, the theoretical limits of silicon material have recently become the bottleneck for the performance of the power devices. By contrast, some wide bandgap (WBG) semiconductor-based devices are competitive, one of which is the enhancement-mode (E-mode) Gallium Nitride (GaN) high electron mobility transistor (HEMT), showing a high breakdown voltage and small parasitic input and output capacitances. However, the strict limitations of the gate-to-source voltage, the different mechanism of reverse conduction, and the extra parasitic inductance and capacitance bring a lot of challenges in driving E-mode GaN HEMTs.

To resolve t...[ Read more ]

Due to the high reliability, low cost and high availability, silicon-based MOSFETs are widely used for power management integrated circuits (PMICs). Nevertheless, the theoretical limits of silicon material have recently become the bottleneck for the performance of the power devices. By contrast, some wide bandgap (WBG) semiconductor-based devices are competitive, one of which is the enhancement-mode (E-mode) Gallium Nitride (GaN) high electron mobility transistor (HEMT), showing a high breakdown voltage and small parasitic input and output capacitances. However, the strict limitations of the gate-to-source voltage, the different mechanism of reverse conduction, and the extra parasitic inductance and capacitance bring a lot of challenges in driving E-mode GaN HEMTs.

To resolve these issues, in this thesis, the characteristics of GaN HEMTs are analyzed first, followed by the introduction of the driving scheme for GaN-based power converters and the review of the state-of-the-art functional blocks. Based on the prior art, an innovative half-bridge gate driver for a bi-directional buck/boost converter with GaN HEMTs is proposed. With the target to protect the rectifier and achieve the near-optimal dead-time control, a three-level driving circuit and a dead time controller are designed separately, assisted by the level shifters and bootstrapping circuit.

The proposed design is implemented using GlobalFoundries 0.18μm BCD-Lite process. To reduce the effect of the parasitic parameters, different PCB layout designs are analyzed, among which the optimal one is applied to the board. Simulation and experiment results show that the gate-drive signals can achieve three levels to protect the corresponding device, and the dead time has less than 3ns deviation from the optimal point in the 9MHz applications. Furthermore, the use of the dead time controller can elevate the efficiency by up to 8.33% and 6.87% at light load in a buck and a boost converter, respectively.