The explosion of versatile computation-intensive applications, such as real-time video/image processing, autonomous driving and artificial intelligence, promotes the rapid development of specialized hardware accelerators to meet huge computation demands and strict energy requirements. Among various accelerators, Field-Programmable Gate Arrays (FPGAs) have gained popularity due to their fast processing speed, excellent power efficiency, high flexibility and low cost. Despite these advantages, programming on FPGAs is non-trivial since it takes great efforts and requires the expertise in hardware architecture to write low-level register-transfer level (RTL) codes. To reduce the design effort, high-level synthesis (HLS) design methodology, which automatically synthesizes behavioral descript...[ Read more ]

The explosion of versatile computation-intensive applications, such as real-time video/image processing, autonomous driving and artificial intelligence, promotes the rapid development of specialized hardware accelerators to meet huge computation demands and strict energy requirements. Among various accelerators, Field-Programmable Gate Arrays (FPGAs) have gained popularity due to their fast processing speed, excellent power efficiency, high flexibility and low cost. Despite these advantages, programming on FPGAs is non-trivial since it takes great efforts and requires the expertise in hardware architecture to write low-level register-transfer level (RTL) codes. To reduce the design effort, high-level synthesis (HLS) design methodology, which automatically synthesizes behavioral descriptions in C/C++ into RTL designs, is developed and becoming a superior alternative to RTL methods for its higher productivity. However, as the abstraction level increases, it is challenging to generate high-quality FPGA designs with current HLS tools. In this thesis, we tackle a series of crucial issues existing in HLS tools and present a collection of HLS-based frameworks to generate high-performance FPGA designs automatically. First, we investigate how to select the most suitable HLS directives efficiently to maximize design performance given certain hardware constraints. HLS tools rely on the use of synthesis directives/pragmas to generate digital designs meeting a set of specifications. However, the selection of suitable directives is challenging, depending largely on designer experience and knowledge of the target architecture and digital design. To solve this problem, we propose a comprehensive model-based analysis framework, COMBA, which is capable of analyzing the effects of a multitude of directives and finding a near-optimal directive configuration efficiently. As resource utilization ratios increase, routing becomes another crucial problem in FPGA design. Routing congestion degrades design performance and even leads to implementation failures. Early and accurate congestion prediction in HLS is of great benefit to identify routability oriented bottlenecks in the source code and guide the performance optimization in HLS. To this end, we propose a machine learning based framework to predict routing congestion in HLS and map the expected congested regions in the design to the relevant source code. By locating congested regions, routing congestion can be resolved easily. Finally, we focus on a real-world complicated application, stereo vision, and propose an HLS-based domain-specific design flow, FP-Stereo, for building high-performance stereo vision pipelines on FPGAs automatically. Diverse stereo vision methods are supported and effective approaches are proposed to fully exploit parallelism, efficiently utilize resources, and adequately ensure usability. Detailed analysis is provided as guidance for designers to select the right design choice which achieves an appropriate balance among accuracy, speed and hardware cost.