With the increase of integration and complexity within systems-on-chip (SoC) and widely explored high-performance computing multicore systems, the power consumption of processors has grown rapidly. Dynamic voltage and frequency scaling (DVFS) has emerged as a popular technique to save energy by adaptively adjusting the voltage and frequency of processors according to their workloads. Frequency scaling takes only a handful of CPU cycles, however, voltage scaling usually happens on a millisecond or microsecond scale. Therefore, voltage scaling remains to be the bottleneck to achieve fine-grained DVFS, which exploits the slack time more effectively and saves more power. This thesis research will be focused on the design and implementation of buck converters with fast reference tracking spe...[ Read more ]

With the increase of integration and complexity within systems-on-chip (SoC) and widely explored high-performance computing multicore systems, the power consumption of processors has grown rapidly. Dynamic voltage and frequency scaling (DVFS) has emerged as a popular technique to save energy by adaptively adjusting the voltage and frequency of processors according to their workloads. Frequency scaling takes only a handful of CPU cycles, however, voltage scaling usually happens on a millisecond or microsecond scale. Therefore, voltage scaling remains to be the bottleneck to achieve fine-grained DVFS, which exploits the slack time more effectively and saves more power. This thesis research will be focused on the design and implementation of buck converters with fast reference tracking speed.

The first prototype, a 10-MHz current-mode hysteretic-controlled buck converter with fast reference tracking capability for DVFS application, verifies the effectiveness of single-on/-off reference tracking with turning-point output voltage (TPOV) prediction. The proposed TPOV prediction has the advantages of achieving near-optimal reference tracking with fast tracking speed and negligible output voltage undershoot or overshoot. Moreover, parasitic effects and different load types, especially one emulating a real DVFS-enabled processor, are considered. The prototype is fabricated in a 0.13-μm CMOS process. The chip achieves nearly optimal reference tracking over a wide output voltage range and with various steps. It also demonstrates a state-of-the-art FOM for tracking speed and is proved to be competitive for fine-grained DVFS application.

The first prototype is focused on the controller design for achieving optimal reference tracking. To speed up the reference tracking further, the second design aim to optimize the power stage with smaller passive components. The second prototype, a 25-MHz fast transient adaptive-on/off-time controlled three-level buck converter with flying-capacitor voltage calibration, is demonstrated. Three-level buck converter is chosen as it can handle higher input voltage and reduces the inductor and capacitor significantly. The control scheme of adaptive-on/ off-time is employed and proves to be more advantageous than the conventional PWM control thanks to its self-balance mechanism on the flying-capacitor voltage. An extra calibration loop is added to eliminate the error caused by the non-idealities. TPOV prediction is also utilized to achieve near-optimal single-on/-off reference tracking. Turning-point output voltage is derived with the fast and power-efficient equation circuit. The higher switching frequency, the three-level structure together with the TPOV prediction ensure the reference tracking of buck converters to meet the demand of fine-grained DVFS applications. Furthermore, precise DCM operation with the switching frequency adapted to the load current is proposed, which enhances the light load efficiency of the three-level buck converter.

Since the two prototypes are both hysteretic-controlled, a systematic analysis tool was developed to investigate hysteretic-controlled DC-DC converters. Compared with switching averaging technique, non-linear control theory is more accurate to describe the behaviour of hysteretic-controlled converters. As a result, hysteretically controlled converters are modelled with Tsypkin locus, which is a technique for analysing nonlinear systems. The modelling facilitates the design of the feedback network and the determination of other essential parameters of a hysteretic controller. Moreover, both the steady state performance and stability of a hysteretically controlled buck converter are accurately predicted by the modelling. Thus, the modelling provides stability-oriented design guidelines to the circuit designers.