This thesis is divided into two parts. The first part deals with designing an integrated wireless power transfer receiver for biomedical implants, and the second part deals with the design of radiation-hardened memory circuits for space applications.

For the first part of this research, we recognize that wireless power transfer (WPT) through an inductive link can provide convenient and reliable power to implantable medical devices (IMDs) for biomedical applications. The WPT system consists of a power transmitter and a power receiver. The power receiver consists of a secondary coil in parallel with a resonating capacitor. For a conventional design, the parallel-resonant circuit drives a rectifier that converts the AC voltage to DC voltage, and the rectifier is then cascaded with a volta...[ Read more ]

This thesis is divided into two parts. The first part deals with designing an integrated wireless power transfer receiver for biomedical implants, and the second part deals with the design of radiation-hardened memory circuits for space applications.

For the first part of this research, we recognize that wireless power transfer (WPT) through an inductive link can provide convenient and reliable power to implantable medical devices (IMDs) for biomedical applications. The WPT system consists of a power transmitter and a power receiver. The power receiver consists of a secondary coil in parallel with a resonating capacitor. For a conventional design, the parallel-resonant circuit drives a rectifier that converts the AC voltage to DC voltage, and the rectifier is then cascaded with a voltage regulator to provide a stable DC voltage for supplying power to downstream electronics. This research focuses on the design of the power receiver in reducing the reverse current of the rectifier and enhancing the power conversion efficiency (PCE). The resonant frequency is chosen to be 40.68 MHz to minimize the size of the secondary coil, and all integrated circuits are designed using 0.13-μm CMOS processes. First, a digital-control on-off delay-compensated 40.68 MHz full-wave active rectifier is proposed. It consists of two NMOS active diodes and a cross-coupled PMOS transistor-pair. High efficiency is achieved by eliminating turn-on delay, reverse current, and multiple pulsing using digital techniques. The measured maximum voltage conversion ratio (VCR) is 0.97, and the measured maximum PCE is 93.2% for a 500 Ω load resistance. Second, an on-off delay-compensated 40.68 MHz active full-wave rectifier with an embedded voltage-doubler is proposed. A conventional full-wave rectifier consists of four diodes, yet the proposed full-wave rectifier with embedded voltage-doubler consists of only two active diodes, with one using a PMOS and the other a NMOS power transistor. The measured maximum VCR is 1.91, and the maximum PCE is 91.9% for a load resistance of 200 Ω. Third, a 40.68 MHz one-stage 2X/0X reconfigurable resonant regulating (R³) rectifier is proposed. AC to DC rectification and voltage regulation are achieved in one stage using only two power MOS transistors. Mode-switching is realized through PWM control, and Type-II compensation is used to achieve fast transient response. The output voltage is regulated at 1.2 V. The measured PCE reaches up to 90.7%. The measured undershoot and overshoot are lower than 95 mV, and the settling time is less than 25 μs when the load switches between 1.2 mA and 12 mA.

The second part of the research focuses on designing radiation-hardened circuits for space applications. In space, if a voltage pulse (generated due to radiation particles striking the integrated circuit) is larger than the switching threshold of the logic circuit, data at the sensitive node may get flipped, leading to a single-event upset (SEU). This research focuses on the design of radiation-hardened circuits for memory cells. Due to positive feedback in a conventional 6T SRAM cell, a change in the state of one storage node (due to SEU) causes the other storage node to change, ultimately flipping the state of the cell. Hence, the traditional SRAM cell should be modified such that it can retain its state even if the stored data get flipped by an SEU or SEMNU (single-event multi-node upset). Therefore, a soft-error-aware 14T (SEA14T) SRAM cell, which can fully recover from SEUs of both polarities induced at any single sensitive node, is proposed. The proposed cell also addresses the issue of the single-event multi-node upset as it exhibits soft-error recovery at the internal node-pair.