CMOS technology scaling enables high density IC integration and fast transistor operation. However, it brings rising concern about Low Frequency Noise (LFN) for the circuits such as CMOS image sensors (CIS) and flash memory cells which are demanding on signal-to-noise ratio (SNR) and reliability. It is well known that LFN results from the cumulative effect of a large number of traps that distributed inside the MOSFET oxide or at the silicon-oxide interface with different energy level respectively. The drain current fluctuation amplitude due to the trapping and de-trapping events from a single oxide trap increases with the shrinking device geometry. Buried Channel (BC) MOSFETs are widely known to have lower LFN than normal Surface Channel (SC) MOSFETs due to the reduced interaction betwe...[ Read more ]

CMOS technology scaling enables high density IC integration and fast transistor operation. However, it brings rising concern about Low Frequency Noise (LFN) for the circuits such as CMOS image sensors (CIS) and flash memory cells which are demanding on signal-to-noise ratio (SNR) and reliability. It is well known that LFN results from the cumulative effect of a large number of traps that distributed inside the MOSFET oxide or at the silicon-oxide interface with different energy level respectively. The drain current fluctuation amplitude due to the trapping and de-trapping events from a single oxide trap increases with the shrinking device geometry. Buried Channel (BC) MOSFETs are widely known to have lower LFN than normal Surface Channel (SC) MOSFETs due to the reduced interaction between channel carrier and the silicon-oxide interface. It is commonly seen that BC MOSFETs are used as source followers for Charge-Coupled Device (CCD) and CMOS image sensors.

In this thesis, we have designed and fabricated deep BC MOSFETs with the voltage rating of 5 V which is commonly used in CIS design. The 1/f^γ LFN is found due to non-uniform space and energy distributed oxide traps. The slope factor y decreases with a more negative gate biasing voltage. To comprehensively explain the BC MOSFETs noise spectrum, we developed an LFN model based on the Shockley--Read--Hall (SRH) theory with WKB tunneling approximation. It is the first time that the 1/f^γ LFN spectrum of BC MOSFET is numerically analyzed and modeled. The trapping current amplitudes of each oxide traps are extracted efficiently with the Impedance Field Method (IFM). Our new model counts the noise contribution from each discretized oxide trap in oxide mesh grids. Experiments verify that the new model matches well the noise power spectrum from 10 Hz to 10 kHz with various gate biasing conditions from accumulation to weak inversion.