Power devices based on wide-bandgap (WBG) semiconductors such as gallium nitride (GaN) (especially in the form of lateral high electron mobility transistor, HEMT) and silicon carbide (SiC) possess the intrinsic capability to deliver more favorable specific on-resistance/blocking-voltage trade-off, faster switching speed, and higher operating temperature than the mainstream Si counterparts. Recently, the WBG power devices have witnessed rapid deployment in consumer, industrial, and automotive electronics markets. To assure reliability characterizations of WBG power devices at both the device and circuit levels are required for continuous technology advancement and process optimization. Such characterization is extremely challenging because dynamic electrical parameters exhibit very quick recovery behavior with very short transient times, and thus require faster characterization techniques. This thesis focuses on high-speed characterization of WBG power devices using advanced testing techniques.
The first part is devoted to characterizing the dynamic R
ON of commercial high-voltage p-GaN gate power HEMTs with an Ohmic-type or a Schottky-type gate metal/p-GaN contact, using an optimized active MOSFET-based voltage clamping circuit. The characterization methodologies are profound and comprehensive, including double-pulse and multi-pulse tests and statistical verification. Moreover, the results are significant for optimizing gate drive design for p-GaN gate power devices. We found that the dynamic R
ON of Schottky-type p-GaN gate power HEMT shows a strong dependence on gate drive voltage (V
GS) under the hard-switching condition. A higher V
GS from 5 V to 7 V can suppress the dynamic R
ON by ~17% because the dynamic R
ON induced by the positively shifted V
TH under high drain bias stress can be eliminated. Meanwhile, the maximum V
GS of Schottky-type p-GaN gate power HEMTs should also be kept no more than 7 V to ensure long-term gate reliability. In addition, the dynamic R
ON of Ohmic-type p-GaN gate power HEMTs (or HD-GIT) also shows a strong dependence on gate injection current (I
G). A larger I
G at the ON state from the p-GaN gate stack facilitates a faster de-trapping process of electR
ON traps and thus results in a smaller dynamic R
ON, but it also significantly increases the gate drive losses. Therefore, an I
G or V
GS close to the upper limit of the suppler’s recommended range should be taken as the optimum gate driving condition to minimize the dynamic R
ON of p-GaN gate power devices.
The second part proposed a novel testing setup for high-speed characterization of dynamic V
TH, which is a behavior unique to Schottky-type p-GaN gate HEMTs and unseen in Si and SiC power MOSFETs. The newly developed testing setup is referred to as a bootstrap voltage clamping circuit, in which the GaN HEMT serves as the key bootstrapping device in the voltage clamping circuit. This new testing setup delivers a state-of-the-art OFF-to-ON (or stress-to-sense) delay (T
delay) of 60 ns, enabling the characterization of dynamic V
TH under the high-frequency switching stress conditons with a maximum switching frequency (fSW) up to 2 MHz. In addition, it also fulfills a variety of testing requirements, such as providing a wide OFF-state static stress time (T
stress) from 0.5 µs to 399 s (or longer) and supporting a wide range of OFF-state drain bias (V
DSQ) up to the voltage rating of high-voltage GaN power HEMTs. The dynamics of the V
TH shift in 650-V Schottky-type p-GaN gate HEMT under high-frequency switching, different V
DSQ, short-and long-term static stress conditions, and various case temperatures are systematically investigated using this new testing technique. Furthermore, the long-term stress schemes including DC stress and high-frequency switching stress, and memory-saving data acquisition strategies are presented in detail. A motherboard/daughterboard testing configuration is proposed to flexibly measure multiple samples. The dynamic V
TH characteristics of commercial low-voltage p-GaN gate power HEMTs are comprehensively characterized under the long-term DC stress and long-term high-frequency switching stress, using the bootstrap voltage clamping circuit and proposed testing schemes. The dynamic V
TH shifts in p-GaN gate power HEMTs should be taken as critical electrical parameters for optimizing the gate drive design to fully exploit the potential of GaN power HEMTs.
The last part focuses on the development of an all-WBG 650-V/84-mΩ GaN/SiC cascode power device to combine the unique merits of high-mobility channel in lateral GaN heterojunction and P-N junction-enabled voltage blocking capability in vertical SiC structures. A low-voltage p-GaN gate power HEMT provides a high-mobility two-dimensional electR
ON gas (2-DEG) channel and enables normally-off control, while high-voltage normally-on SiC JFET provides high-voltage blocking and avalanche breakdown capability. The GaN/SiC cascode device makes up for the shortcomings of GaN power HEMTs by exhibiting avalanche capability, negligible dynamic R
ON degradation, and dynamic V
TH shift under high drain bias stress. Compared with SiC MOSFETs and Si/SiC cascode devices, GaN/SiC cascode devices show faster-switching speed, lower switching loss, greatly improved thermal stability in V
TH. Furthermore, it is found that the avalanche capability of the GaN/SiC cascode power device is intrinsically enabled by the avalanche breakdown of gate-to-drain junction diode (D
GD) of HV SiC JFET, using an unclamping inductive switching circuit. The 650-V/84-mΩ GaN/SiC can withstand a maximum single-pulse UIS energy (E
UIS) up to 162.3 mJ without degradation. A slightly higher E
UIS of 198.8 mJ results in the channel activation of SiC JFET during the avalanche breakdown process and the increase of intrinsic gate resistance of SiC JFET (R
G,SiC) by a factor of 24.9 after the avalanche breakdown. It is further found that the channel of SiC JFET can be activated at the beginning of the avalanche breakdown process with the help of a 15-V Zener diode in parallel with the low-voltage GaN HEMT. The initially activated channel can undertake a large part of UIS energy, and thus release the burden imposed on D
GD of SiC JFET and achieve a larger E
UIS up to 342.7 mJ.
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