The steady classical scaling of the planar metal-oxide-semiconductor field-effect-transistor (MOSFET) has been the major motivation for the semiconductor industry over the past few decades. However, classical scaling with the planar MOSFET devices beyond 22 nm technology is extremely challenging due to the ever-increasing leakage currents and undesirable short channel effects. Complementary metal oxide semiconductor (CMOS) scaling is enabled by FinFET devices at the 22nm technological node. FinFET device suppresses the sub threshold leakage currents by regaining better electrostatic control over the silicon channel with a high-k metal gate as compared to the planar MOSFET device. However, the effectiveness of the ultimately scaled FinFET device is doubtful for maintaining the performanc...[ Read more ]

The steady classical scaling of the planar metal-oxide-semiconductor field-effect-transistor (MOSFET) has been the major motivation for the semiconductor industry over the past few decades. However, classical scaling with the planar MOSFET devices beyond 22 nm technology is extremely challenging due to the ever-increasing leakage currents and undesirable short channel effects. Complementary metal oxide semiconductor (CMOS) scaling is enabled by FinFET devices at the 22nm technological node. FinFET device suppresses the sub threshold leakage currents by regaining better electrostatic control over the silicon channel with a high-k metal gate as compared to the planar MOSFET device. However, the effectiveness of the ultimately scaled FinFET device is doubtful for maintaining the performance and packing density of the integrated circuits (ICs) with the technology scaled to beyond sub-7nm regime. For example, the processor launched by the Apple for mobile applications (Apple A12) uses FinFET devices in 7nm technology with a transistor density of 96.5Mtr/mm², is 4.3% lower as compared to the transistor density of the Intel’s 10nm processor. Hence there is a need for identifying possible novel MOS device structures for improving the performance and the integration density beyond 7nm technology.

Gate-all-around (GAA) metal-oxide-semiconductor (MOS) devices are the new innovations in the silicon process technologies that can be considered as a potential candidate to replace the FinFET devices due to their promising ways to address the scalability issues by exhibiting better short channel characteristics. The geometry of the GAA device enhances the electrostatic control and hence the scalability of the drawn gate length. The competition between FinFET and GAA technologies is fierce at 5nm technology targeting the performance and transistor density. Some of the major players in the semiconductor industry like Global Foundries, TSMC, and ST Microelectronics has reported the design rules for using the GAA devices in 5nm technology.

This work explores the potential GAA device architectures for the upcoming 5 nm node and beyond by benchmarking the performance of the GAA devices with FinFET device at 5nm technological node with the aid of technology computer–aided design (TCAD) three-dimensional (3D) simulations. Potential minimum sized GAA device structures are identified and characterized for the low power and high-performance applications. Possible nanosheet device structures are identified in gate-all-around technology at 5nm node. Electrical characteristics like active power consumption, propagation delay, and leakage power consumption of various test circuits designed in GAA technology are benchmarked with the FinFET technology.

The latter part of this work explores the idea of asymmetric counter doped MOSFETs for mitigating the subthreshold leakage currents and improving the ION/IOFF with gate all around technology (GAA). Novel SRAM cell with asymmetrically counter-doped source / drain diffusion gate all around nanosheets is proposed in this work. The proposed 6T SRAMs with counter doped pull up and access devices in the GAA technology exhibits superior characteristics in terms of data stability and leakage power consumption as compared to the symmetrical 6T SRAMs. TCAD simulations of 4KB 6T SRAM array suggest that the static noise margin (SNM) of the SRAM cell with GAA technology can be increased by up to 44.4% with counter doping profile of 3E19/cm³ while delivering the read delay close to the symmetrical SRAMs. Results reveal that the adoption of optimized counter doped stacked nanosheets can offer up to 37.6% improvement in level 1 (L1) cache read stability and a 9.2% reduction in level 2 (L2) cache write power consumption, while delivering similar write noise margins close to symmetric FinFET-based caches. Furthermore, some important ideas and plans for addressing the challenges in the design of cache memory is described as a plan for the future research..