THESIS
2022
1 online resource (ix, 53 pages) : illustrations (some color)
Abstract
Homomorphic encryption schemes usually involve huge modular exponentiation
operations. Thus, improving the efficiency of modular exponentiation for large
exponents is a real-world issue. Modular exponentiation is computed by a series
of modular multiplications. However, performing a series of modular multiplications
is computationally expensive. This paper proposes hardware/software
co-design for efficient modular exponentiation. In this work, we first explore
the use of particle swarm optimization (PSO) for the modular exponentiation
in software, and discuss an efficient hardware co-design utilizing an FPGA. Our
findings reveal that the suggested PSO approach surpasses all other deterministic
and non-deterministic approaches already in use. Further, we also demonstrate
a comprehensive...[
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Homomorphic encryption schemes usually involve huge modular exponentiation
operations. Thus, improving the efficiency of modular exponentiation for large
exponents is a real-world issue. Modular exponentiation is computed by a series
of modular multiplications. However, performing a series of modular multiplications
is computationally expensive. This paper proposes hardware/software
co-design for efficient modular exponentiation. In this work, we first explore
the use of particle swarm optimization (PSO) for the modular exponentiation
in software, and discuss an efficient hardware co-design utilizing an FPGA. Our
findings reveal that the suggested PSO approach surpasses all other deterministic
and non-deterministic approaches already in use. Further, we also demonstrate
a comprehensive analysis for the optimal performance and parameter selection
of our proposed PSO approach. Finally, we implement homomorphic encryption
schemes, such as RSA and Paillier, using our PSO-based hardware/software
co-design. Our approach gains resource savings for 1024-bit as follows: RSA
encryption/decryption - 60.7% (area) and 65.3% (DSP); Paillier encryption -
46.3% (area) and 40% (DSP) and Paillier decryption - 73.7% (area) and 66.6%
(DSP). We have obtained area-time improvements of 1024-bit as follows: RSA
encryption/decryption - 2.7x; Paillier encryption - 2x and Paillier decryption -
4.6x using Xilinx Virtex-7 FPGAs.
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