THESIS
2021
1 online resource (xvi, 103 pages) : illustrations (some color)
Abstract
Reducing CMOS interconnect capacitance brings an overall improvement to circuit
performance by suppressing delay, crosstalk, and power consumption. It
becomes the key to continued improvement in advanced technology nodes, to
address the increasing capacitance from the densely packed metal lines. The integration
complexity in modern ICs also calls for longer interconnections, further
exaggerating the benefit of capacitance reduction measures.
Theoretically, an effective dielectric constant of 1 is the minimum capacitance of
CMOS back-end-of-line (BEOL) interconnect, with only air as the dielectric material.
As mechanical concerns render it impractical, we utilize an air-gap technology
to approach a mostly-air dielectric environment surrounding coupled interconnections,
achieved by patte...[
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Reducing CMOS interconnect capacitance brings an overall improvement to circuit
performance by suppressing delay, crosstalk, and power consumption. It
becomes the key to continued improvement in advanced technology nodes, to
address the increasing capacitance from the densely packed metal lines. The integration
complexity in modern ICs also calls for longer interconnections, further
exaggerating the benefit of capacitance reduction measures.
Theoretically, an effective dielectric constant of 1 is the minimum capacitance of
CMOS back-end-of-line (BEOL) interconnect, with only air as the dielectric material.
As mechanical concerns render it impractical, we utilize an air-gap technology
to approach a mostly-air dielectric environment surrounding coupled interconnections,
achieved by patterning an interconnect layer into air and dielectric regions.
This requires a precise pattern transfer from a mask to the fabricated structures.
An hBN-capped air-gap process is proposed, taking advantage of the processing
techniques and material properties of hBN at atomic thickness. Electrical and
mechanical reliability concerns in BEOL are addressed, including Young's modulus,
the
flatness of the air-gap capping layer, and resistance to moisture uptake,
with further improvement by air-gap capping layer engineering.
The applications of the proposed air-gap technology at intra- and inter-metalization
layers are discussed. In reducing the intra-layer adjacent-line capacitance, we extend
the use of air-gaps to the upper metalization layers. A large void-to-metal-spacing
ratio results in a capacitance reduction of 50%. For global interconnections,
it translates to a 72% reduction in the energy-delay product. To further
reduce capacitance in the inter-layer above and below an interconnect line, we
demonstrate the patterning of a dielectric layer into pillar structures. The overall
large-area κ
eff is lowered from 4.2 of SiO
2 to 2.1, while κ
eff of a narrow line is
projected at 1.5. Finally, an integration strategy integrating void regions in both
intra- and inter-metal for a hollow mostly-air interconnect structure is discussed,
which yields an ultralow-κ
eff of 1.36.
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