A unified and comprehensive method is proposed to generate all possible topologies of switched-capacitor converters (SCCs) with N flying capacitors that work in 2- to (N+1)-topological phases. The topologies include both step-up and step-down converters, with voltage-conversion ratios (VCRs) that are integers and rational numbers. Ladder diagrams are introduced to illustrate the operation of SCCs, and duality can be applied to generate step-down SCCs from step-up SCCs, (m/n)X SCCs from (1–m/n)X SCCs for step-down converters, and (n/m)X from (n/(n–m))X SCCs for step-up converters, and vice versa. Criteria are set to identify and eliminate redundant topologies. The exhaustive search identifies SCCs with VCR_min and VCR_max that are better than 1/2^NX and 2^NX respectively.

Switched-capacito...[ Read more ]

A unified and comprehensive method is proposed to generate all possible topologies of switched-capacitor converters (SCCs) with N flying capacitors that work in 2- to (N+1)-topological phases. The topologies include both step-up and step-down converters, with voltage-conversion ratios (VCRs) that are integers and rational numbers. Ladder diagrams are introduced to illustrate the operation of SCCs, and duality can be applied to generate step-down SCCs from step-up SCCs, (m/n)X SCCs from (1–m/n)X SCCs for step-down converters, and (n/m)X from (n/(n–m))X SCCs for step-up converters, and vice versa. Criteria are set to identify and eliminate redundant topologies. The exhaustive search identifies SCCs with VCR_min and VCR_max that are better than 1/2^NX and 2^NX respectively.

Switched-capacitor converters are then compared based on their slow switching limit resistance (R_SSL) and fast switching limit resistance (R_FSL) that are computed systematically using matrix analysis, which could serve as efficient design guideline.

Based on the analysis, a fully-integrated reconfigurable SCC that achieves very small voltage conversion ratios (VCR = 1/4X, 1/5X, 1/6X) is designed using a 65nm CMOS process. For each of the topologies, the SCC is designed to have the minimum output resistance, and the optimal design achieved 50% improvement in power density compared to a conventional Dickson SCC, which is verified by measurement results.

A second 3-interleaving-phase fully-integrated 1/4X SCC is also designed. To fully utilize all capacitors, the problem of idling capacitors is solved by the novel capacitor bridging and phase expansion techniques. The drain-source flipping problem associated with reconfigurable switches is solved by a phase clamping technique. The current density is improved by 25% comparing to the traditional 3-phase 1/4X SCC without sacrificing efficiency; and the improvement is also verified by measurement results.