Complementary metal–oxide–semiconductor (CMOS) process is the most fundamental technology for nowadays digital circuit. To combine digital front-end with Radio Frequency (RF) front-end in a wireless transceiver (TRX), different building blocks for RF front-end such as low-noise amplifier (LNA), voltage-controlled oscillator (VCO), mixer and phase-locked loop (PLL) have also been demonstrated in CMOS for many years. However, power amplifier (PA) is still the main obstacle for full integration of wireless transceiver due to low supply voltage, degrading the performance including output power and efficiency. With the introduction of 5th generation wireless communication technology (5G), the performance requirements of PA are even stricter because of millimeter-wave (mmWave) frequency band...[ Read more ]

Complementary metal–oxide–semiconductor (CMOS) process is the most fundamental technology for nowadays digital circuit. To combine digital front-end with Radio Frequency (RF) front-end in a wireless transceiver (TRX), different building blocks for RF front-end such as low-noise amplifier (LNA), voltage-controlled oscillator (VCO), mixer and phase-locked loop (PLL) have also been demonstrated in CMOS for many years. However, power amplifier (PA) is still the main obstacle for full integration of wireless transceiver due to low supply voltage, degrading the performance including output power and efficiency. With the introduction of 5th generation wireless communication technology (5G), the performance requirements of PA are even stricter because of millimeter-wave (mmWave) frequency band and modulation signal with high peak-to-average power ratio (PAPR).

In this thesis, a CMOS 3-way Doherty PA operated in 5G New Radio frequency range 2 (5G NR FR2) has been designed to improve the power-added efficiency (PAE) in deep power-back off (PBO) region. The design considerations and details will be discussed. The impedance scaling network is replaced by transformer, which also act as a balun for differential end to single end transformation, and the quarter-wavelength transmission line (QWL) impedance inverter is implemented by CLC π-network for compact area.

Post-layout simulation result shows that the proposed power amplifier achieves 19.8dBm output power with peak PAE 21.7% at 1.8V supply voltage at 27GHz. The PAE at 6dB PBO and 12dB PBO are 13.8% and 8.1% respectively.