In this study, a method to fabricate vertically stacked SiNW from bulk-Silicon technology is demonstrated. Multiple stacked SiNW with diameters down to 10nm are successfully fabricated by utilizing the 0.5um process at the Nano Fabrication Facility combined with the Bosch cycle-Inductively Couple Plasma (ICP) etch system and time-controlled thermal oxidation. It is shown that the silicon pillar with sub-100nm scalloped sidewall roughness after ICP etch and oxidation conditions are the major processing parameters in forming successful stacked SiNW. A physical based stress analytical study combined with Deal-Grove model based simulation is performed to extend the optimization and process repeatability on the cross-section evolution stacked SiNW. A process characterization on ICP etching o...[ Read more ]

In this study, a method to fabricate vertically stacked SiNW from bulk-Silicon technology is demonstrated. Multiple stacked SiNW with diameters down to 10nm are successfully fabricated by utilizing the 0.5um process at the Nano Fabrication Facility combined with the Bosch cycle-Inductively Couple Plasma (ICP) etch system and time-controlled thermal oxidation. It is shown that the silicon pillar with sub-100nm scalloped sidewall roughness after ICP etch and oxidation conditions are the major processing parameters in forming successful stacked SiNW. A physical based stress analytical study combined with Deal-Grove model based simulation is performed to extend the optimization and process repeatability on the cross-section evolution stacked SiNW. A process characterization on ICP etching on scalloped pillar which control the final core shapes also performed to model the sidewall on the effect. Based on the analytical and empirical results, a method to fabricate vertically stacked SiNW transistor is proposed by using the available equipments at HKUST.