With the constantly growing Internet traffic and development of broadband access technologies such as DSL, cable modem, and gigabit Ethernet, future broadband packet switches/routers should be able to support a large number of connection ports for at least the following two reasons: a) the number of Internet access points is still rapidly increasing; and b) the development of optical transmission technologies makes a huge number of communication channels available. Both facts impose a challenge to the router’s scalability with regard to the increasing number of network flows and switching ports. In addition, routers are also required to be able to provide Quality-of-Service (QoS) at the surge of triple-play services (data, voice and video) in Next-Generation-Networks (NGN). In this thes...[ Read more ]

With the constantly growing Internet traffic and development of broadband access technologies such as DSL, cable modem, and gigabit Ethernet, future broadband packet switches/routers should be able to support a large number of connection ports for at least the following two reasons: a) the number of Internet access points is still rapidly increasing; and b) the development of optical transmission technologies makes a huge number of communication channels available. Both facts impose a challenge to the router’s scalability with regard to the increasing number of network flows and switching ports. In addition, routers are also required to be able to provide Quality-of-Service (QoS) at the surge of triple-play services (data, voice and video) in Next-Generation-Networks (NGN). In this thesis, we try to address this switching ports/network flows scalability issue and design the routers with QoS support as well.

The two main router components we are investigating are: the switch fabric and the memory subsystem. We start from the Space-Memory-Space switch design paradigm that provides QoS relatively easily, and then use the Clos-interconnection to scale its space parts. By making all memories fully shared (in a distributed way), we show that the Central-stage Buffered Clos-network (CBC namely) are scalable in terms of not only the hardware cost, but the complexities of scheduling algorithms as well. To scale the router’s memory subsystem, we introduce parallelism into current SRAM/DRAM combination solutions and design a Parallel Hybrid SRAM/-DRAM (PHSD namely) buffering system. By a series of simple yet efficient memory management algorithms, we show that the PHSD can significantly outperform previous solutions by reducing both the packet delay and the costly requirement on SRAM.