With the anticipation of increasing system demands, the need to integrate multiple functions (e.g. digital, analog, high voltage, etc.) on a single chip has become apparent. PICs (power integrated circuits), which combine high-voltage, high-current output devices with low-voltage logic and control elements, have provided better performance and reliability, and reduced cost and system size compared to the discrete approach. A major issue for the design of this kind of circuits is the substrate cross-talk between adjacent power and CMOS devices, which prevents normal operation of the circuits. The issue becomes more severe in automotive applications, in which a high temperature environment is usually involved....[ Read more ]

With the anticipation of increasing system demands, the need to integrate multiple functions (e.g. digital, analog, high voltage, etc.) on a single chip has become apparent. PICs (power integrated circuits), which combine high-voltage, high-current output devices with low-voltage logic and control elements, have provided better performance and reliability, and reduced cost and system size compared to the discrete approach. A major issue for the design of this kind of circuits is the substrate cross-talk between adjacent power and CMOS devices, which prevents normal operation of the circuits. The issue becomes more severe in automotive applications, in which a high temperature environment is usually involved.

The commonly used isolation techniques in PICs are the traditional p-n junction isolation (JI) and the dielectric isolation (DI). But JI still requires large silicon area, and the electrical isolation is rather poor. Although the superiority of DI offered by SOI (silicon-on-insulator) technology results in a much smaller chip area and minimum leakage current, the higher wafer cost and lower heat dissipation capability limit it only to niche applications.

In this paper, a novel bulk silicon isolation structure with wafer-thick, front-back trench is proposed for automotive (42V) power integrated circuit (PIC) applications. This technique provides the advantages of complete isolation with lower wafer cost and higher thermal dissipation capability compared with the silicon-on-insulator (SOI) technology. Experimental results show that the novel isolation structure can provide complete electrical isolation and a 13% reduction in the thermal resistance compared to the SOI technology. In addition, this novel isolation technology offers a potential cost reduction of 5X to 10X compared to the SOI technology.