Compared with other types of Analog-to-Digital converters (ADCs), delta-sigma analog-to-digital converters (ΔΣ ADCs) are more tolerant to analog circuit imperfections. Benefiting from the development of modern VLSI technologies, ΔΣ converters have shown good performance in applications where the bandwidths are relatively low. Meanwhile, recent interests in the wireless RF transceivers have focused on high levels of integration and adaptability to support multiple communication standards. Together with the proliferation of broadband communication system, a large dynamic range ΔΣ ADC with a wide bandwidth is therefore required....[ Read more ]

Compared with other types of Analog-to-Digital converters (ADCs), delta-sigma analog-to-digital converters (ΔΣ ADCs) are more tolerant to analog circuit imperfections. Benefiting from the development of modern VLSI technologies, ΔΣ converters have shown good performance in applications where the bandwidths are relatively low. Meanwhile, recent interests in the wireless RF transceivers have focused on high levels of integration and adaptability to support multiple communication standards. Together with the proliferation of broadband communication system, a large dynamic range ΔΣ ADC with a wide bandwidth is therefore required.

This thesis describes the design of two ΔΣ AD converters. The first one, which is designed for UHF RFID reader, uses MASH 2-1-1 architecture while the second one uses a single-loop multi-bit structure. Both of them are targeted at a similar specification of achieving an effective number of bit (ENOB) larger than 12-bit within a bandwidth of 1~2MHz. Both designs are discussed from architectural level designs to circuit level implementations. An experimental prototype for the first one was designed and fabricated in 0.18-μm CMOS process with an active area of 1.5mm². The achievable dynamic range at 24 oversampling ratio is 72dB with a bandwidth of 1.28MHz and the total power consumption of 19.9mW. The second one was designed in 0.13-μm CMOS process and the ADC core occupies an active area of only 0.43 mm². In simulation, the single-loop multi-bit ΔΣ converter achieves a peak SNDR of about 86 dB for a bandwidth of 1.56MHz while consumes only 5.66mW power. Finally, comparison between the two designed ΔΣ converters is made and the conclusion is given.