The Gas Identification System (GIS) based on an array of gas sensors and its recognition techniques has been widely investigated in recent decades. However, the integration of GIS together with gas sensing has yet to be demonstrated. After acquiring the data from the sensor array, pattern recognition algorithms are essential to discriminate between different gases. The algorithms of the reported GIS are usually very complex and computationally expensive, commonly implemented by software in personal computers (PCs). The conventional GIS is typically expensive, to consume much power and is hardly integrated in one single chip. The decision trees (DT) classification algorithm is a well-known efficient pattern recognition method. However, little work has been done on it for the hardwa...[ Read more ]

The Gas Identification System (GIS) based on an array of gas sensors and its recognition techniques has been widely investigated in recent decades. However, the integration of GIS together with gas sensing has yet to be demonstrated. After acquiring the data from the sensor array, pattern recognition algorithms are essential to discriminate between different gases. The algorithms of the reported GIS are usually very complex and computationally expensive, commonly implemented by software in personal computers (PCs). The conventional GIS is typically expensive, to consume much power and is hardly integrated in one single chip. The decision trees (DT) classification algorithm is a well-known efficient pattern recognition method. However, little work has been done on it for the hardware implementation of GIS.

In this thesis, a novel low-power compact classifier based on the DT algorithm for GIS is designed and presented. Compared with the previous work, this proposed solution presents a good trade-off between hardware complexity and classification accuracy. The classifier is based on a decision tree implemented as a single layer of threshold logic units(TLUs) followed by a programmable binary tree implemented using combinational logic circuits.

Moreover, for multiplication expensive processing such as pattern classification and image processing, digital parallel multiplication is analyzed and designed. A novel unified implementation of signed/unsigned multiplication is proposed using a simple sign-control unit together with a line of multiplexers.