THESIS
2010
xvii, 121 p. : ill. (some col.) ; 30 cm
Abstract
Pipelined ADCs are widely used in portable devices because of its fast speed and medium resolution. In a pipelined ADC, capacitor mismatch and finite amplifier gain will lead to linear and non-linear error in pipeline stages. Digital calibration methods have been developed to compensate for the linear errors inside pipeline ADC. However, there is no effective digital calibration method to compensate non-linear error yet....[
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Pipelined ADCs are widely used in portable devices because of its fast speed and medium resolution. In a pipelined ADC, capacitor mismatch and finite amplifier gain will lead to linear and non-linear error in pipeline stages. Digital calibration methods have been developed to compensate for the linear errors inside pipeline ADC. However, there is no effective digital calibration method to compensate non-linear error yet.
In this thesis, the calibration techniques of pipelined ADC are systematically studied. A new interpolation-based non-linear calibration method on low-power pipeline ADC is proposed. A skip-and-fill algorithm is introduced to the system to form a background calibration. The methodology of designing an effective non-linear digital calibration scheme for pipeline ADC with non-linear error is also included in this thesis. In the end, a low-power pipelined ADC architecture with an optimal non-linear calibration is formed.
Based on this architecture, a 12-bit 20MS/s pipelined ADC is designed. The design is simulated and fabricated in 0.35μm CMOS process. Both simulation results and measurement results show the interpolation-based non-linear calibration can recover the pipelined ADC from 7-bit resolution (41.3dB) to 12-bit resolution (72.5dB).
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