In modern CMOS image sensors (CIS), benefited from technology scaling, the CIS pixel pitch has been continuously reduced to increase pixel density and spatial resolution. However, reduction in pixel pitch would also reduce the in-pixel photosensing area and lead to degradation in CIS performance such as sensitivity, signal-to-noise ratio (SNR), etc. Thus the conventional CIS active pixel, which is characterized by one photodiode, three transistors and four interconnections in pixel, becomes extremely difficult to maintain good image quality as pixel size shrinks due to its low fill factor. A lot of researches have been done to achieve CIS with smaller pitch and at the same time to increase the fill factor. The most common way to achieve this is to reduce the number of in-pixel transisto...[ Read more ]

In modern CMOS image sensors (CIS), benefited from technology scaling, the CIS pixel pitch has been continuously reduced to increase pixel density and spatial resolution. However, reduction in pixel pitch would also reduce the in-pixel photosensing area and lead to degradation in CIS performance such as sensitivity, signal-to-noise ratio (SNR), etc. Thus the conventional CIS active pixel, which is characterized by one photodiode, three transistors and four interconnections in pixel, becomes extremely difficult to maintain good image quality as pixel size shrinks due to its low fill factor. A lot of researches have been done to achieve CIS with smaller pitch and at the same time to increase the fill factor. The most common way to achieve this is to reduce the number of in-pixel transistors by sharing some of the transistors with 2-4 neighboring pixels.

In this thesis, we demonstrated a novel scheme enabling the use of the in-pixel photosensing diode itself to perform the reset operation and hence avoiding the need of an extra reset transistor, as is the case in conventional three-transistor active pixel sensor (3T-APS) architecture. This results in a new compact and high fill factor 2T-APS structure. To further reduce the transistor count inside a pixel and achieve ultimate aim of 1T-APS architecture, the select transistor is eliminated using a specific pixel reset voltage control. To our knowledge, this is the world’s first reported CMOS photodiode type APS that only contains one transistor per pixel.

Both proposed 2T-APS and 1T-APS have been fabricated with a commercially available 0.35μm CMOS technology to demonstrate their functionalities. The both resulting 2T and 1T pixels have the same pitch of 7μm including the guard ring with fill factors of 38% and 46%, respectively. The pixel characteristics and design tradeoff are presented and discussed.