Recent advances in semiconductor fabrication technology have enabled the concept of a single camera-on-a-chip, which integrates all camera functions onto a single piece of silicon. To enable the concept of low cost and high performance miniature camera-on-a-chip, the proposed research aims at developing advanced real-time digital image processing (DIP) cores or modules that could be integrated together with the photo-sensing pixel array. The developed DIP cores will satisfy the stringent requirements of compactness and low-power real-time operation to enable their integration into a variety of low cost portable consumer imaging products.

In this work, we first present a multi-precision reconfigurable multiplier which incorporates variable precisions, parallel processing, razo...[ Read more ]

Recent advances in semiconductor fabrication technology have enabled the concept of a single camera-on-a-chip, which integrates all camera functions onto a single piece of silicon. To enable the concept of low cost and high performance miniature camera-on-a-chip, the proposed research aims at developing advanced real-time digital image processing (DIP) cores or modules that could be integrated together with the photo-sensing pixel array. The developed DIP cores will satisfy the stringent requirements of compactness and low-power real-time operation to enable their integration into a variety of low cost portable consumer imaging products.

In this work, we first present a multi-precision reconfigurable multiplier which incorporates variable precisions, parallel processing, razor-based dynamic voltage scaling (DVS), and dedicated multi-precision operands scheduling to realize full energy and performance flexibility and efficiency at both system and hardware levels. According to user's arbitrary requirements (eg. throughput), the dynamic voltage and frequency scaling management unit first configures the multiplier operating at the proper precision and frequency. Adapting to the run-time workload of the targeted application, razor flip-flops and the dithering voltage unit then help the voltage and frequency scaling management unit to autonomously configure the multiplier to work at the minimum possible power operating point to achieve the lowest power consumption. This multi-precision multiplier is then augmented by an operands scheduler which can analyze and rearrange the input data to help to find the best voltage and frequency combinations to further reduce the overall power consumption. Our work successfully demonstrates through a fabricated prototype that multi-precision architecture can reap the benefits from the dynamic voltage scaling technique more effectively enabling efficient use for DIP applications.

Considering our goal of enabling the concept of low-power real-time miniature camera-on-a-chip, a new digital image sensor (DPS) architecture is then proposed, which uses 2T DRAM as the storage element and adopts multi-reset integration methodology in order to reduce both the memory needs, the sensor size and the sensor's power consumption in the pixel level. The operation of the DPS takes advantage from the chronological change of the code, which results in reduced memory needs without affecting the light resolution. In the proposed implementation, a 4-bit in-pixel memory is used to reduce the pixel size, and an 8-bit resolution is achieved with multi-reset scheme. In addition, full complementary metal-oxide-semiconductor (CMOS) 2T DRAM and selective refresh scheme are adopted to implement the memory elements and further increase the area savings. Proposed architecture is validated by a prototype chip fabricated using AMS 0.35μm CMOS technology. Our scheme makes the design of 20% fill factor and 22μm x 22μm digital pixel sensor possible, and the current consumption per pixel is also improved compared to previous implementations.

Finally, we push our idea to its extreme - reduce the image capture precision and the image processing precision to 1 single bit. The resulted binary images and corresponding Boolean operations can highly reduce the computational complexity of DIP cores/modules compared to the trditional full-precision arithmetic processing. Besides, the design takes advantage of typically long integration times of each image plane in order to run the processing circuit during integration and at very low operating frequency and supply voltage, and realize zero-time ultra-low-power image processing. To validate our proposed scheme, a novel bit-plane-based local-voting early-stop Hough transform algorithm is impmlemented into a VLSI prototype. Our parallel architecture shows an 8 times speedup compared to existing architectures. The hardware implementation of our proposed algorithm is realized on a Xilinx Virtex-4 FPGA board. Experimental results demonstrate that our proposed algorithm greatly reduces the computation load, improves the processing efficiency and reduces the power consumption while maintaining the accuracy to an acceptable level.