At the mobile multi-media age, high resolution flat-panel displays are becoming the central feature of many consumer products. Functional circuit blocks monolithically integrated with the pixel thin-film-transistors (TFTs) on the same display panel, i.e., system-on-panel (SOP), paints a new picture of ubiquitous consumer products. It has been difficult to achieve the desired memory hierarchy for SOP due to the process restrictions set by the panel material. Different memory structures from direct-write memory, like DRAM, to storage-class memory, like FLASH, have been demonstrated on panel. Memory performances, however, are found to deteriorate due to the low-temperature process for SOP. Phase-change memory (PCM), an emerging memory technology, offers a new set of features combin...[ Read more ]

At the mobile multi-media age, high resolution flat-panel displays are becoming the central feature of many consumer products. Functional circuit blocks monolithically integrated with the pixel thin-film-transistors (TFTs) on the same display panel, i.e., system-on-panel (SOP), paints a new picture of ubiquitous consumer products. It has been difficult to achieve the desired memory hierarchy for SOP due to the process restrictions set by the panel material. Different memory structures from direct-write memory, like DRAM, to storage-class memory, like FLASH, have been demonstrated on panel. Memory performances, however, are found to deteriorate due to the low-temperature process for SOP. Phase-change memory (PCM), an emerging memory technology, offers a new set of features combing the fast write of DRAM and the non-volatility of FLASH. In this thesis, we have demonstrated the integration of PCM technology with TFT drivers to provide a fast and reliable non-volatile memory for SOP.

Phase-change element (PCE) stores information based on the PC material’s property to reversibly change between two resistive states with Joule heating. The required Joule heat to program the PCE can be reduced by scaling its dimensions. However, 1μm is the current technology node for TFT technology, which falls far behind the single crystalline silicon technology (22nm). To overcome the low current drive and coarse design rule in TFT technology, thermal engineering to concentrate the thermal energy is applied to achieve PCE programming at a low programming current. PCE programming can be achieved with 10% of the programming current and half programming voltage by our proposed PCE structure of that by their conventional counterpart.

To access individual PCEs for reading and writing, each PCE should be in series connected to a driver. Important performance parameters for PCE driver selection, including cell size, current drive, disturb immunity, power consumption and scalability, are investigated using 3-D numerical device simulations. Among various possible choices, PN diodes and vertical Gate-All-Around MOSFETs are picked as potential PCE driver to study in detail since they represent distinct classes of devices. Simulation results suggest that PN diodes show superiority in technology nodes with large device dimensions. Therefore, thin-film-diodes (TFDs) are firstly investigated as PCE driver in terms of both process compatibility and device characteristics. Although the TFDs exhibit larger driving capability than convention TFTs, it is noted that the TFTs are made with thick gate oxide (45nm), which is common for TFT technology to prevent early breakdown on rough poly-Si film. We demonstrated reliable 15nm thin oxide on smoother poly-Si film prepared by metal-induced-lateral crystallization (MILC). With the development of the thin oxide, a simple one-time-programmable memory with 10⁶ on/off ratio is also demonstrated on TFT technology. Furthermore, a modified MILC on pre-defined narrow lines together with thin oxide is used to improve the current drive of TFTs even superior over the thin-film-diodes.

Finally, multi-Fin TFTs are paired with PCEs and are laid out in NOR architecture to build the PCM test array. The RESET/SET resistance read window of the fabricated test array can be maintained at 60 after 10⁵ programming cycles and with a 10-year retention time at 390K.