Thin-film transistors (TFTs) based on zinc oxide (ZnO) are being hotly pursued as replacements of silicon-based TFTs for displays and other transparent electronic applications recently. There is a demand for fast-switching TFTs in mobile devices requiring high resolution or highly integrated active-matrix flat-panel displays. One way to improve the switching speed of the TFTs is to reduce the RC delay of the TFTs circuit. Self-aligned structure of ZnO TFT with hydrogen doped source/drain is presently employed due to its’ low parasitical resistance and capacitance.

Because of the rapid diffusion of hydrogen in ZnO, the use of boron, phosphorus and arsenic, the heavier and more slowly-diffusing dopants, are systematically investigated as a replacement of hydrogen. N-type conduc...[ Read more ]

Thin-film transistors (TFTs) based on zinc oxide (ZnO) are being hotly pursued as replacements of silicon-based TFTs for displays and other transparent electronic applications recently. There is a demand for fast-switching TFTs in mobile devices requiring high resolution or highly integrated active-matrix flat-panel displays. One way to improve the switching speed of the TFTs is to reduce the RC delay of the TFTs circuit. Self-aligned structure of ZnO TFT with hydrogen doped source/drain is presently employed due to its’ low parasitical resistance and capacitance.

Because of the rapid diffusion of hydrogen in ZnO, the use of boron, phosphorus and arsenic, the heavier and more slowly-diffusing dopants, are systematically investigated as a replacement of hydrogen. N-type conduction was obtained for these elements doped ZnO. A lowest resistivity of 2mΩ-cm has been obtained at a boron dose of 10¹⁶/cm². The resistivity of P-doped ZnO is generally ~3 times smaller than that of As-doped ZnO. Self-aligned, top-gated ZnO TFTs with S/D regions doped with implanted B, P and As are shown to be more stable than those doped with hydrogen. Except boron, short channel length can be easily achieved when device source/drain using P or As. Thus phosphorus is found to be the optimum dopant for the self-aligned ZnO TFTs, since the phosphorus doped ZnO exhibits relative low resistivity and slow diffusion of phosphorus in ZnO.

Fluorination, the other way to improve the electrical characteristics of the ZnO TFTs, is developed as the traps passivation of the poly-crystalline ZnO. Firstly, the dependence of the extent of the improvement on the amount of fluorine, precisely controlled using ion implantation, is investigated. At a fluorine concentration of 10²⁰/cm³, transistors with a relatively high field-effect mobility of ~60cm²/Vs have been realized. Fluorine concentration in excess of 10²⁰/cm³ is found to result in degraded transistor characteristics. Secondly, Plasma-immersion doping, a technique more compatible with the processing of large-area glass substrates, is investigated as a replacement of ion implantation for fluorination. Because less damage is induced in the channel of a transistor by the bombardment of the ions, enhancement-mode transistors with a relatively high field-effect mobility of ~71cm²/Vs, a lower drain leakage current and improved reliability have been realized.

Hysteresis in the current-voltage characteristics of a ZnO TFT has been studied. Electric dipoles at the interface of the dielectric and the channel have been proposed as the agents responsible for the hysteresis. The application of the device as a memory element has been investigated and demonstrated. The origin of the hysteresis in the ZnO TFTs is proposed mainly attributed to the water diffusing into the channel of the device. Protection of a transistor against moisture-exposure using a passivation layer is critical in ensuring long-term operational stability of the transistor. Devices free of hysteresis have been fabricated using a fabrication process modified to minimize exposure to moisture and to drive out absorbed water in the channel of the transistor.

Finally, a novel transparent multi-touch panel based on the active-matrix ZnO TFTs is explored. Compared to the passive-matrix projected capacitive multi-touch, the presented panel exhibits higher resolution (pixel size is less than 1mm × 1mm) and hence high touch precision due to the high sensitivity of self capacitive sensing and the small parasitic capacitance. Therefore, the panel might be suitable for the precise pen handwriting, touch area sensing, and even the fingerprint scanner.