The 60-GHz worldwide unlicensed band provides up to 9-GHz bandwidth and thus enables Gb/s-data-rate point-to-point communication links and high-definition video transfer. However, implementations of circuits and systems at this frequency range are still quite challenging. This dissertation is dedicated to the design and demonstration of a high-performance 4-path 60-GHz phased-array receiver front-end (RFE) in CMOS technology with novel ideas at both system architecture and circuit implementation.

At the circuit level, several novel design techniques for the key building blocks were demonstrated. First, a 24-GHz and 60-GHz dual-band standing-wave VCO with mode-switching technique was designed in 0.13μm CMOS process. Second, a bimodal transformer-based enhanced magnetic tuning...[ Read more ]

The 60-GHz worldwide unlicensed band provides up to 9-GHz bandwidth and thus enables Gb/s-data-rate point-to-point communication links and high-definition video transfer. However, implementations of circuits and systems at this frequency range are still quite challenging. This dissertation is dedicated to the design and demonstration of a high-performance 4-path 60-GHz phased-array receiver front-end (RFE) in CMOS technology with novel ideas at both system architecture and circuit implementation.

At the circuit level, several novel design techniques for the key building blocks were demonstrated. First, a 24-GHz and 60-GHz dual-band standing-wave VCO with mode-switching technique was designed in 0.13μm CMOS process. Second, a bimodal transformer-based enhanced magnetic tuning technique was proposed to implement a quadrature VCO (QVCO) in 65nm CMOS process with an ultra-wide frequency tuning range from 48.8 GHz to 62.3 GHz (corresponding to 24 % tuning range at 60GHz) and figure-of-merit (FoM) of 181 to 184 dBc. Third, to operate the QVCO in a phased-lock loop (PLL), a harmonic-boosting technique with 4^th-order LC tank was proposed to achieve a divide-by-4 injection-locked frequency divider with state-of-the-art frequency locking range (LR) from 58.5 GHz to 72.9 GHz (21.9 % at 60GHz) and figure-of-merit (FoM) of 6.5 GHz/mW.

Furthermore, an LO generation scheme was proposed to generate LO signals with required phase shifts for a 4-path phased-array receiver. Circuit techniques include highly linear phase shifters, wide-locking-range frequency tripler, and successive-approximation phase tuning algorithm. Implemented in 65nm CMOS, the LO generation measures linear phase range larger than -90° ~ 90°, amplitude variation less than ±0.35dB, phase resolution of 22.5°, and phase error smaller than 1.5°.

Finally, at the system level, a 4-path phased-array receiver front-end system was designed and integrated in a 65-nm CMOS process. With proposed hybrid-mode mixing scheme, the system performance (in terms of linearity, noise figure, gain, power consumption, and chip area) is significantly improved as compared to existing solutions. In addition, modified successive algorithm is proposed for automatic phase calibration and gain equalization to achieve beam-forming with maximum peak-signal-to-noise ratio of more than 28dB.