As Silicon complementary-oxide-semiconductor (CMOS) devices scale into the sub-22nm regime, severe short channel effects and power-dissipation constraints lead to huge challenges. To maintain high switching speed and lower power consumption, III-V high mobility channel materials are currently under intensive investigation due to the high electron injection velocity. Although tremendous advances are being made, the grand challenges, such as the lack of a reliable metal/high-k gate stack, large device footprint, parasitic resistance and capacitance, still hinder a viable III-V technology for logic applications. The major objective of this dissertation is to experimentally explore deeply scaled high performance InGaAs buried channel MOSFETs on Silicon substrates....[ Read more ]

As Silicon complementary-oxide-semiconductor (CMOS) devices scale into the sub-22nm regime, severe short channel effects and power-dissipation constraints lead to huge challenges. To maintain high switching speed and lower power consumption, III-V high mobility channel materials are currently under intensive investigation due to the high electron injection velocity. Although tremendous advances are being made, the grand challenges, such as the lack of a reliable metal/high-k gate stack, large device footprint, parasitic resistance and capacitance, still hinder a viable III-V technology for logic applications. The major objective of this dissertation is to experimentally explore deeply scaled high performance InGaAs buried channel MOSFETs on Silicon substrates.

Firstly, oxide/InAlAs interface quality was optimized by surface pretreatment and passivation. InGaAs surface channel and recessed-gate buried channel MOSFETs were fabricated. Improved device performance was achieved with the buried channel architecture. However, it was still limited by the large parasitic resistance, gate-recess etching process and long channel length. Source/drain (S/D) selective regrowth is a promising technique to solve these problems.

The second part of this dissertation focuses on the development of a gate-last process incorporating selective S/D regrowth. Sub-micron channel-length devices were achieved with this process by optimizing the optical lithography and lateral over-etching. The impact of vertical scaling of gate dielectric and device active layers was investigated. A low-temperature post metallization annealing process was developed to achieve enhancement-mode (E-mode) operation. The optimized device fabrication process resulted in high-performance 120nm E-mode InGaAs MOSFET on GaAs substrate with a record-high transconductance of 1881 mS/mm at V_ds=0.5V.

By further optimizing the fabrication process, 30nm E-mode InGaAs MOSFET on Silicon substrates was successfully demonstrated with a high transconductance of 1697 mS/mm at V_ds=0.5V and a record-low on-resistance of 157 Ω·μm. To the best of our knowledge, this is the first high-performance III-V MOSFET with channel length down to sub-50nm. Benchmarking of logic figures of merit with state-of-the-art InGaAs MOSFETs in literature was then presented. Our devices exhibited highly competitive performance, indicating that combining buried InAlAs/InGaAs quantum-well channel with S/D regrowth is promising for future low-power logic applications.