THESIS
2012
xiii, 67 p. : ill. ; 30 cm
Abstract
A switching fabric is a key component in a router. Its performance has a great impact on the overall performance of a router. In this thesis, we examine three important topics related to the design of a high-speed switching system....[
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A switching fabric is a key component in a router. Its performance has a great impact on the overall performance of a router. In this thesis, we examine three important topics related to the design of a high-speed switching system.
The first issue we examine is the optimal buffer allocation between input and output ports in a crossbar switch. Buffers used in high speed switches usually need be custom made and can be very expensive. Fortunately we can use the buffers we have more efficiently, i.e., performance of the switch can be greatly improved by wisely allocating the buffers we have at the input and output ports. In the thesis, an analytical model is built to solve the problem of buffer allocation. Simulations are also performed to verify the validity of the model.
The second issue we study is how to pipeline the scheduling algorithm of an AWG (Arrayed Waveguide Grating) based optical crossbar switch. Optical switching has been receiving more and more research interest recently due to its advantages over traditional electronic switching in several aspects. AWGs are commonly used as the switching fabric. Crosstalk will be introduced if several ports use the same wavelength simultaneously, and this can be limited by scheduling. In the thesis, a new scheduling scheme, which pipelines the iterations, is proposed. Simulations show that this scheme can give much better delay performance than existing algorithms, especially when there is a stringent time limit.
Another switching related issue we study is the scalability of an AWG switch. As the switch size grows, multi-stage architecture must be used. Scheduling for such switches is the most challenging issue. In the thesis, a three stage optical switching architecture together with a fast scheduling algorithm is proposed. Simulation is used to evaluate the performance of the proposed architecture.
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