THESIS
2013
xix, 143 p. : ill. ; 30 cm
Abstract
Digitally-intensive RF design has attracted a lot of attention recently because it is
highly programmable for multi-standard operation and enables high system integration
with digital baseband and application processors on the same die. Moreover, many RF
impairments could be repaired by using digital calibration.
This thesis presents a 65nm all digital polar transmitter with on chip LO generation,
polar modulation and power amplification for WCDMA and WLAN application.
In the LO path, an all-digital phase lock loop (ADPLL) is designed for low noise
and low spur carrier generation. To reduce the out-band phase noise, a quadrature phase
digitally-controlled oscillator (QDCO) with quantization noise suppression technique is
proposed and measured 6.6dB improvement of the out-ba...[
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Digitally-intensive RF design has attracted a lot of attention recently because it is
highly programmable for multi-standard operation and enables high system integration
with digital baseband and application processors on the same die. Moreover, many RF
impairments could be repaired by using digital calibration.
This thesis presents a 65nm all digital polar transmitter with on chip LO generation,
polar modulation and power amplification for WCDMA and WLAN application.
In the LO path, an all-digital phase lock loop (ADPLL) is designed for low noise
and low spur carrier generation. To reduce the out-band phase noise, a quadrature phase
digitally-controlled oscillator (QDCO) with quantization noise suppression technique is
proposed and measured 6.6dB improvement of the out-band phase noise. The in-band
phase noise of the ADPLL is minimized by using a statistical TDC with ultra-fine time
resolution and a proposed phase-interpolated ΣΔ programmable divider
To reduce the DCO pulling effects, a quadrature output ÷1.5 divider is proposed for
the LO frequency plan. This ÷1.5 divider employs 8-phases harmonic rejection mixing
and duty-cycle correction techniques to minimize its output I-Q mismatch. For Wideband
and fine-resolution phase modulation, a 2-segments phase-interpolated ΣΔ digital
phase modulator is employed with bandwidth extension and phase error calibration
techniques.
In the AM path, a novel digital polar amplifier with switched-capacitor modulator
and high linear PA-array is proposed to achieve the output power range for the target
applications. A linearization technique is implemented by adaptively changing the PA
bias voltage according to the RF envelope. Even without amplitude pre-distortion, the
transmitter system measures RMS-EVM of 2.83% and 4.07% for WCDMA and WLAN
54-Mb/s 64-QAM OFDM respectively while providing a peak output power of
20.4dBm with PAE 32.3%.
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