Mobile and portable applications have become the driving force behind the growth of the Complementary Metal-Oxide Semiconductor (CMOS) image sensor's industry. Low power and increased resolution CMOS image sensor design is becoming a requirement and yet a challenge for mobile and portable application's segment of the market. This thesis presents a number of data conversion related circuit and algorithm techniques to reduce the power consumption of the CMOS image sensor System-on-a-Chip (SoC).

The first part of this thesis focuses on energy efficient Successive-Approximation-Register (SAR) Analog-to-Digital Converter (ADC) architectures. A new pilot-Digital-to-Analog-Converter (pDAC) technique with mixed-signal Forward Error Correction (FEC) is proposed to reduce the SAR DAC's...[ Read more ]

Mobile and portable applications have become the driving force behind the growth of the Complementary Metal-Oxide Semiconductor (CMOS) image sensor's industry. Low power and increased resolution CMOS image sensor design is becoming a requirement and yet a challenge for mobile and portable application's segment of the market. This thesis presents a number of data conversion related circuit and algorithm techniques to reduce the power consumption of the CMOS image sensor System-on-a-Chip (SoC).

The first part of this thesis focuses on energy efficient Successive-Approximation-Register (SAR) Analog-to-Digital Converter (ADC) architectures. A new pilot-Digital-to-Analog-Converter (pDAC) technique with mixed-signal Forward Error Correction (FEC) is proposed to reduce the SAR DAC's figure-of-merit (FoM) from 61.3 fJ/step to 39.8 fJ/step with no appreciable deterioration in linearity and thermal noise.

The need for compact circuit area in CMOS image sensors is addressed by a novel hybrid SAR Single Slope (SS) ADC. A 12b SAR-SS ADC with improved pDAC is presented followed by a self-calibrated 13b Successive-Approximation-Single-Slope (SASS) ADC with 43 minimum-sized unit capacitors. The proposed calibration does not require Least-Mean-Square (LMS) data fitting.

The second half of this thesis seeks to further improve the efficiency of image sensors by utilizing the spatial redundancy between neighbouring pixels. A low-complexity Address-Event-Representation Block Coding (AERBC) algorithm based on Visual-Pattern-Image-Coding (VPIC) is proposed to perform image compression in AER pixel arrays. Only 0.0625 comparisons and 0.125 subtractions are performed for each pixel and on average 30.82 dB PSNR can be achieved at 1.0 bit-per-pixel (bpp) code rate.

Last but not least, a mixed-signal implementation of the VPIC algorithm is designed for an Active-Pixel-Sensor (APS) array. The number of quantization is decimated by the proposed compression algorithm and the ADC power consumption is reduced accordingly. In the image compression mode, the total energy consumption per pixel is one third of that in the raw data mode while the frame-rate is quadrupled under the same clock frequency. Results from fabricated chips illustrate that the prospect of low power consumption while increasing the sensor's resolution is achievable for future generation of portable CMOS image sensors.