ZnO-based thin-film transistors (TFTs) have become attractive for use as driving devices in flat-panel display application, due to their high mobility and large area uniformity. Bottom-gate structures have been widely studied. However, this structure is unsuitable for the integration of peripheral circuits for the system on panel and realization of high resolution, large size, and low cost flat-panel display, due to their high parasitic capacitance and poor scalability. _{2 3 2 2 3}...[ Read more ]

ZnO-based thin-film transistors (TFTs) have become attractive for use as driving devices in flat-panel display application, due to their high mobility and large area uniformity. Bottom-gate structures have been widely studied. However, this structure is unsuitable for the integration of peripheral circuits for the system on panel and realization of high resolution, large size, and low cost flat-panel display, due to their high parasitic capacitance and poor scalability.

A novel Al₂O₃/SiO₂ gate dielectric structure is developed for realizing self-aligned top-gate ZnO TFT. The charge trapping at the interface between the channel layer and the gate dielectric is minimized due to the Al₂O₃ protective layer deposited immediately on top of the ZnO layer in the same sputtering chamber without breaking the vacuum. Additionally, self-aligned top-gate ZnO TFTs with Al₂O₃ deposited by sputtering as gate dielectric showed high electrical performance, including field-effect mobility of 27 cm²/Vs and subthreshold swing of 0.12 V/decade.

Self-aligned top-gate amorphous indium gallium zinc oxide (a-IGZO) TFTs with SiN_x/SiO₂/SiN_x/SiO₂ passivation layers are developed. The source/drain regions were hydrogen-doped by CHF₃ plasma during the over-etching of gate dielectric. SiO₂/Al₂O₃ stack gate dielectric was used to produce high performance a-IGZO TFTs, such as subthreshold swing of 0.2 V/decade.

Self-aligned top-gate a-IGZO TFTs with source/drain regions doped by implanted phosphorus and arsenic are developed, respectively. The proposed a-IGZO TFTs showed much better thermal stability, as compared with those with S/D regions formed by hydrogen or argon plasma treatment. Litter change of the threshold voltage and subthreshold swing were observed after heat-treatment at 200 °C for 1 hour.

Finally, GaN thin films are utilized as active channel layer to produce n-type TFTs. GaN thin films were deposited by reactive dc magnetron sputtering technique at different substrate temperature. The bottom-gate GaN TFTs with SiO₂ as gate dielectric exhibit good electrical performance, including field-effect mobility of 5 cm²/Vs, on/off current ratio of 6×10⁶, and subthreshold swing of 0.4 V/decade. The GaN TFTs have great potential in the application of next generation flat-panel display.