There is an increasing demand for electronic devices with smaller sizes, higher performances and increased functionality. The formation of vertical interconnects or through silicon vias (TSV) may be one of the approaches to provide the integration of logic, memory and other functional integrated circuits.

The TSVs are filled with copper by electroplating method. Although many researches have been done to achieve void-free TSV plating, there are also many technical issues needs to be solved for copper filling process including low throughput, high cost (makes up nearly 40% of the overall TSV cost), heavy overburden and consistent void-free filling.

In this study, the copper plating of TSVs with the diameter and the depth in the ranges of 10-30 μm and 50-150 μm, were investigate...[ Read more ]

There is an increasing demand for electronic devices with smaller sizes, higher performances and increased functionality. The formation of vertical interconnects or through silicon vias (TSV) may be one of the approaches to provide the integration of logic, memory and other functional integrated circuits.

The TSVs are filled with copper by electroplating method. Although many researches have been done to achieve void-free TSV plating, there are also many technical issues needs to be solved for copper filling process including low throughput, high cost (makes up nearly 40% of the overall TSV cost), heavy overburden and consistent void-free filling.

In this study, the copper plating of TSVs with the diameter and the depth in the ranges of 10-30 μm and 50-150 μm, were investigated. A super-conformal plating mechanism is developed basic on the electro-chemical behavior of the additives. The principle of the mechanism is explained electro-chemically and proved with full wafer results.

A nearly 100% bottom up plating recipe was also developed in order to achieve void-free and seamless filling. The principle of the pure bottom-up filling mechanism is also discussed. The effects of concentration of copper, acid and additives were optimized to achieve the desired bottom up plating process. Full wafer plating results is also done to prove the industry production capability. The benefits of pure-bottom up plating mechanism are also discussed.

Nevertheless, the reliability of TSV is yet to be fully investigated and understood. In the dissertation, reliability related issues such as protrusion, delamination, and microvoids of TSV were investigated with the adjustment of chemistry in the plating mechanism. The formation of microvoids and the effect of chemistry were also discussed in detail in this paper.

In this study, most electroplating experiment was conducted with an industrial electroplating tool. The void-free and seamless copper deposition results were achieved with minimized overburden. The plated wafer is also able to fulfill the requirement for reliability test and following TSV processes.