Tunneling field-effect transistors (TFETs) based on the quantum interband tunneling are under extensive research. They provide one promising solution for the CMOS power problem due to the fast switching property with sub-60mV/dec subthreshold swing. Experimental studies on the TFETs structures and materials have been reported in literatures. However, the infrastructure for the research and developments of the TFETs technology is incomplete due to the lack of the electronic design automation (EDA) tools which support the TFETs based integrated circuit simulations and designs. This thesis is focused on developing the compact models and the i-MOS platform to fulfill the gap between the TFETs device and circuit designs.

A compact model for TFETs with double-gate and nanowire config...[ Read more ]

Tunneling field-effect transistors (TFETs) based on the quantum interband tunneling are under extensive research. They provide one promising solution for the CMOS power problem due to the fast switching property with sub-60mV/dec subthreshold swing. Experimental studies on the TFETs structures and materials have been reported in literatures. However, the infrastructure for the research and developments of the TFETs technology is incomplete due to the lack of the electronic design automation (EDA) tools which support the TFETs based integrated circuit simulations and designs. This thesis is focused on developing the compact models and the i-MOS platform to fulfill the gap between the TFETs device and circuit designs.

A compact model for TFETs with double-gate and nanowire configurations is developed in this thesis. With understandings of TFETs operations, unique properties of TFETs and their geometry dependences are identified. The source depletions and channel inversions responsible for the sub-60mV/dec subthreshold swing and the exponential segment in the output curves of TFETs are considered. A closed form solution of the tunneling current is proposed, capturing the main device physiys as well as reducing the computation complexity based on SPICE simulation considerations. A 100/0 channel charge partition scheme is proved based on which the terminal charge model is formulated to describe the capacitance characteristics. The geometry dependences of the double-gate and nanowire TFETs characteristics are reproduced by the compact model. The diffusive transport in TFETs is modeled by the proposed drain-FET method and source-resistance method. TFETs with the uniaxial strain engineering are also accounted for by combining the compact model and tight-binding simulations of material properties.

To assist the TFETs based circuit designs, the i-MOS platform which serves the purpose of an EDA tool for the TFETs technology is developed. With an internet browser as the user interface, the i-MOS provides services from single device simulations, parameter extractions to circuit simulations. It is powered by the tailored open source Ngspice with the developed TFET model implemented. The web-based simulation system is constructed with the efficiently linked server side and client side programs. Simulations of TFETs based logic gates on i-MOS are demonstrated.