After more than 40 years’ transistor scaling, Si CMOS technology has enabled state-of-the-art microprocessors with large-volume, low-cost production and high-level integration. Meanwhile, InP based transistor technologies have established their niche in performance-driven fields, and continue to play an important role in emerging millimeter wave and terahertz applications. As CMOS scales beyond the 22 nm node, severe short channel effects and power density constraint pose great challenges. Monolithic integration of InP based high-speed transistors on large-diameter Si substrates is attracting growing interest for post-Si digital integrated circuits. Moreover, such integration can pave the way to a new class of hybrid integrated circuits utilizing advanced Si manufacturing platfo...[ Read more ]

After more than 40 years’ transistor scaling, Si CMOS technology has enabled state-of-the-art microprocessors with large-volume, low-cost production and high-level integration. Meanwhile, InP based transistor technologies have established their niche in performance-driven fields, and continue to play an important role in emerging millimeter wave and terahertz applications. As CMOS scales beyond the 22 nm node, severe short channel effects and power density constraint pose great challenges. Monolithic integration of InP based high-speed transistors on large-diameter Si substrates is attracting growing interest for post-Si digital integrated circuits. Moreover, such integration can pave the way to a new class of hybrid integrated circuits utilizing advanced Si manufacturing platform with on-chip interconnects.

In this thesis, heteroepitaxy of InP on Si substrates by metalorganic chemical vapor deposition and its application in InGaAs MOSFETs were studied. The growth of InP on Si has been impeded by the large mismatch in lattice constant and thermal expansion coefficient as well as the difference in crystal polarities. To manage the resultant high-density defects, both blanket heteroepitaxy and selective patterned growth were explored. Device quality epitaxial InP on planar Si using GaAs as an intermediate buffer was firstly investigated. On the InP/GaAs/Si compliant substrates, ultra-high mobility InGaAs quantum wells were grown, along with smooth surface morphology. The fabricated nano-scale InGaAs MOSFETs with source/drain regrowth achieved a logic figure of merit (g_m/SS) up to 14 and record-low on-resistance of 129 Ω∙μm. Combining the two-step growth method used in the aforementioned blanket epitaxy and the defect trapping mechanism in nanopatterned growth, a technique for growing large-area coalesced InP on nanostructured Si substrates was successfully developed. The obtained InP-on-Si (IOS) templates exhibited greatly improved crystalline quality with reduced buffer thickness. Al₂O₃/InP MOS capacitors with low interface states density were demonstrated on the IOS templates.