Wide bandgap group III-nitride (III-N) heterojunction power switching devices, with the inherent high breakdown strength and low on-resistance, are promising candidates for next-generation high-efficiency and compact power conversion systems. As these III-N power devices can be implemented on low-cost and highly scalable Si substrates, they are in position to compete with the mainstream Si power device technologies. Despite tremendous progress in material growth, device fabrication and circuit demonstration, stability issues (primarily arising from interface and bulk traps), stand as the road blockers toward high-volume commercialization and need to be addressed with new processing technologies and structure designs. The origins and behaviors of these traps need to be better un...[ Read more ]

Wide bandgap group III-nitride (III-N) heterojunction power switching devices, with the inherent high breakdown strength and low on-resistance, are promising candidates for next-generation high-efficiency and compact power conversion systems. As these III-N power devices can be implemented on low-cost and highly scalable Si substrates, they are in position to compete with the mainstream Si power device technologies. Despite tremendous progress in material growth, device fabrication and circuit demonstration, stability issues (primarily arising from interface and bulk traps), stand as the road blockers toward high-volume commercialization and need to be addressed with new processing technologies and structure designs. The origins and behaviors of these traps need to be better understood, and appropriate characterization techniques need to be developed to evaluate their impacts on device performance/stability.

This thesis aims at revealing the underlying mechanisms of interface/bulk traps in their influence over threshold-voltage (V_TH) stability, breakdown voltage and dynamic ON-resistance, as well as developing interface/bulk trap characterization techniques well suited for III-N heterojunction devices. Advanced gate dielectric techniques are also developed for achieving high-quality dielectric/III-N interface with low interface trap density.

High-κ (κ~28) LaLuO₃ thin film with excellent thermal-stability (up to 1000 °C) is incorporated into III-N MIS-HEMTs with a gate-dielectric-first process, leading to high channel-modulation efficiency, small hysteresis (ΔV_TH) and alleviated current collapse. Furthermore, a nitridation interfacial-layer technology has been developed based on in situ low-damage remote plasma pre-gate treatment. By removing low-quality native oxide and forming a monocrystal-like nitridation interfacial-layer prior to Al₂O₃ deposition, significant interface trap density reduction, steep subthreshold swing (~64 mV/dec) and small ΔV_TH are obtained. Meanwhile, pulse-mode ΔV_TH extraction and frequency/temperature-dependent C-V techniques are developed to precisely characterize interface traps.

GaN buffer traps are critical to breakdown voltage and dynamic behavior of III-N heterojunction power devices. To identify the energy levels of these traps, thermally stimulated current spectroscopy is implemented to the vertical GaN-on-Si structure for the first time. Along with high-voltage back-gating measurement technique, the dynamics of both donor- and acceptor-like traps have been successfully revealed. The mechanisms of GaN-to-Si vertical leakage, which ultimately limit the device breakdown voltage, are also investigated with temperature-dependent high-voltage C-V characterizations and numerical simulation.