The amount of embedded Static Random-Access Memory (SRAM) is increased to meet the performance requirements in each new microprocessor generation. Reliability of memory circuits is degraded with increasing variability and decreasing power supply voltage in scaled CMOS technologies. Furthermore, a larger memory cache operating at an increased switching frequency consumes higher power, thereby shortening the battery lifetime of portable devices and causing a significant challenge for the cooling of advanced computer systems.

Several novel SRAM circuits are proposed in this dissertation for achieving lower power consumption, stronger reliability, and higher speed in memory subsystems of modern microprocessors. Reducing the voltage swing of bitlines is effective for enhancing the...[ Read more ]

The amount of embedded Static Random-Access Memory (SRAM) is increased to meet the performance requirements in each new microprocessor generation. Reliability of memory circuits is degraded with increasing variability and decreasing power supply voltage in scaled CMOS technologies. Furthermore, a larger memory cache operating at an increased switching frequency consumes higher power, thereby shortening the battery lifetime of portable devices and causing a significant challenge for the cooling of advanced computer systems.

Several novel SRAM circuits are proposed in this dissertation for achieving lower power consumption, stronger reliability, and higher speed in memory subsystems of modern microprocessors. Reducing the voltage swing of bitlines is effective for enhancing the power efficiency and data access speed of SRAM arrays. A new differential latch-type sense amplifier is proposed for high-resolution detection of small voltage transitions on memory bitlines. The read access time and energy consumption of an 8 Kibit SRAM array are reduced by up to 36.1% and 32.4%, respectively, with the new sense amplifier as compared to the conventional sense amplifiers in a 65nm CMOS technology. Long wordlines that are attached to a high number of SRAM bit-cells are driven by large buffers for satisfying the performance requirement of memory. A new wordline driver circuit is proposed for achieving suppressed leakage currents and shorter signal propagation delay in large memory arrays.

Leakage power that is consumed by gigascale clock distribution networks is another important challenge in modern integrated circuits. A novel dual-threshold-voltage 2-phase split-clock distribution network is proposed for achieving lower leakage power consumption without degrading the signal slew rate and switching frequency as compared to a conventional clock distribution network. Three novel level shifters are also proposed for reliable operation with subthreshold input voltages down to 150mV in multi-power-supply-voltage integrated circuits. The new level shifters offer up to 2.3X faster output switching as compared to the previously published voltage level shifters.