Embedded memory circuits are the indispensable parts of modern microprocessors and system-on-chips and dominate the silicon area and power consumption in many applications. The operational reliability of memory circuits primarily depends on proper transistor sizing. Supply voltage scaling is one of the most efficient ways to lower the power consumption. However, maintaining high memory yield at low supply voltages is extremely challenging due to the increased threshold voltage variations.

The dynamic bit-line keeper that degrades the performance of memory circuits and increases power consumption by producing contention current is replaced with data and access dependent keeper in this study. A memory array composed of this proposed keeper is implemented in a 65nm CMOS technology to demo...[ Read more ]

Embedded memory circuits are the indispensable parts of modern microprocessors and system-on-chips and dominate the silicon area and power consumption in many applications. The operational reliability of memory circuits primarily depends on proper transistor sizing. Supply voltage scaling is one of the most efficient ways to lower the power consumption. However, maintaining high memory yield at low supply voltages is extremely challenging due to the increased threshold voltage variations.

The dynamic bit-line keeper that degrades the performance of memory circuits and increases power consumption by producing contention current is replaced with data and access dependent keeper in this study. A memory array composed of this proposed keeper is implemented in a 65nm CMOS technology to demonstrate the effectiveness. Peripheral assist-circuits are widely used in memory arrays to lower the minimum operating voltage at the expense of larger power consumption at higher voltage operations. Several adaptive assist-circuits which are previously proposed to reduce energy overhead, degrade the throughput by increasing the latency. A zero latency adaptive assist-circuit is implemented in a 65nm CMOS process to eliminate the energy overhead during high voltage operation of memory circuits in this study. Read bit-line leakage current typically limits the minimum operating voltage of a memory circuit. We systematically investigated the leakage current components in transistors and proposed a device-circuit co-design scheme to eliminate the bit-line leakage current in subthreshold memory circuits. A test chip is implemented that works down to 140mV and consumes the record lowest leakage power in a 65nm process. Access transistor sizing conflict exists in memory circuits for achieving enhanced data stability and writeability. The sizing conflict becomes worst in advanced multi-gate transistors due to width quantization. We explore several device features to produce direction-dependent on-current to eliminate the conflicting transistor sizing requirements in memory circuits.