THESIS
2016
xii, 73 pages : illustrations ; 30 cm
Abstract
Big data analytics is a hot topic in academia and industry because of its diverse
applications in many domains such as finance and security. However, scrutinizing the tremendous amount of data is far from the capabilities of mainstream
computers. The programmable System-on-Chips (SoC) which accommodates
the CPU cores and FPGA fabric on the same chip offers promising avenues in
processing the huge data sets.
One of the challenges in exploiting the programmable SoC systems is delay
overhead due to moving the data back and forth between CPU cores and FPGA
fabric. The CPU hard cores in programmable SoC often communicate with
the soft IP cores in reconfigurable fabric through some dedicated ports. The
various data paths corresponding to different ports have different performance...[
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Big data analytics is a hot topic in academia and industry because of its diverse
applications in many domains such as finance and security. However, scrutinizing the tremendous amount of data is far from the capabilities of mainstream
computers. The programmable System-on-Chips (SoC) which accommodates
the CPU cores and FPGA fabric on the same chip offers promising avenues in
processing the huge data sets.
One of the challenges in exploiting the programmable SoC systems is delay
overhead due to moving the data back and forth between CPU cores and FPGA
fabric. The CPU hard cores in programmable SoC often communicate with
the soft IP cores in reconfigurable fabric through some dedicated ports. The
various data paths corresponding to different ports have different performance
characterizations which make them suitable for various applications. The first
part of this thesis studies the analytical performance model for transferring
data stored in CPU side to FPGA side and vice versa through all different
communication ports and data paths available in a typical programmable SoC.
In the second part of this thesis, we investigate the efficient methodology and designs for development of big data analytics on CPU/FPGA heterogeneous architectures. The Complex Event Processing as a sophisticated
approach in this area, refers to different mechanisms such as event correlation and event patterns detection for processing multiple events with the goal
of inferring the higher level information. While a simple event may provide
trivial information, combining several events can help in deriving more useful information. The existing hardware designs for complex events detection all
target the explicitly defined events. However, there are many scenarios that
some of the events may not be explicitly known ahead of detection. In this
thesis, we propose a general complex event detection methodology which is
capable to deal with implicitly-defined events. The concepts of dynamic state
machine, and context switching mechanism are introduced and an iterative
and a parallel architecture based on the network of processing elements are
proposed. While the former architecture employs the minimum logic resources
in hardware, the later one exploits the intrinsic parallelism in our proposed
methodology and boosts the performance very much with the cost of occupying larger logic resources. The two proposed architectures were implemented
on a typical CPU/FPGA heterogeneous architecture and evaluated against
several synthetic data streams which prove their effectiveness according to
each design objective.
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