THESIS
2016
xvi, 120 pages : illustrations ; 30 cm
Abstract
Power management integrated circuits (PMICs) process electrical power that flows from the source to the loads through an electronic system. With the proliferation of portable applications, low-cost PMICs that achieve high efficiency and fast transient responses with a high level of integration are in great demand. This research focuses on PMIC techniques of high-performance DC-DC switching converters and wireless power receivers.
The first part of this thesis deals with designing fast-transient DC-DC switching converters. First, DC-DC converters are designed to run at 30 MHz with small inductors and output capacitors to achieve fast transient responses. A high-accuracy delay-compensated ramp generator and two new Type-III compensators are proposed. By adding two feedback paths to a c...[
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Power management integrated circuits (PMICs) process electrical power that flows from the source to the loads through an electronic system. With the proliferation of portable applications, low-cost PMICs that achieve high efficiency and fast transient responses with a high level of integration are in great demand. This research focuses on PMIC techniques of high-performance DC-DC switching converters and wireless power receivers.
The first part of this thesis deals with designing fast-transient DC-DC switching converters. First, DC-DC converters are designed to run at 30 MHz with small inductors and output capacitors to achieve fast transient responses. A high-accuracy delay-compensated ramp generator and two new Type-III compensators are proposed. By adding two feedback paths to a conventional ramp generator, the proposed delay-compensated ramp generator can achieve high accuracy and is insensitive to circuit delays. By using differential difference amplifiers (DDAs), two new Type-III compensators are proposed to reduce the chip area. Second, based on the unique structure of the proposed compensators, an end-point prediction (EPP) scheme is proposed to improve reference-tracking responses; and a hybrid scheme with automatic transient detection and seamless loop transition is proposed to improve load-transient responses. Two prototype chips were fabricated in a standard 0.13 μm CMOS process, and measurement results verify the effectiveness of the proposed techniques.
The second part of this thesis deals with designing efficiency-enhanced wireless power receivers. Active diodes are essential building blocks, and the design challenges are to compensate for the propagation delays of comparators and gate drivers, and to achieve high power conversion efficiency with minimum chip area and off-chip components. First, an adaptive on/off delay-compensation technique is proposed such that the active diodes are insensitive to PVT (process, voltage, temperature) variations and mismatches. As a design example, a fully-integrated active rectifier for biomedical applications was fabricated in a standard 0.35 μm CMOS process. The proposed active rectifier achieves high power conversion efficiency and high voltage conversion ratio over a wide output and loading range. Second, a wireless power receiver using a 3-level reconfigurable resonant regulating (R
3) rectifier is proposed. It improves power conversion efficiency and reduces die area and off-chip components by achieving power conversion and voltage regulation in one stage, using only four on-chip power transistors and one off-chip capacitor. A PWM controller using ramp-stacking technique achieves voltage regulation in the full loading range with fast transient responses. An adaptive sizing method is also employed to further improve the light-load efficiency of the receiver. The proposed receiver was fabricated in a 0.35 μm standard CMOS process. It achieves the highest efficiency, the highest level of integration, the fastest transient responses and the smallest chip area when compared with state-of-the-art designs.
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