Electrochemical impedance spectroscopy (EIS) is an application of biosensors that commonly used in biological sensing area. Performing impedance measurement will involve applying the voltage stimulus and acquiring the signal outcome. Thanks to the low-power consumption and simple circuit architecture, successive approximation register (SAR) ADC is often the major choice for impedance array sensing with moderate resolution and sampling rate. For mixed-signal designs like impedance array sensors, an on-chip processing unit is normally required. Designing a processing system using hardware description language (HDL) allows a fast-paced system design and verification while enhancing the processing unit function.

In this work, the design of an efficient SAR ADC for an impedance array senso...[ Read more ]

Electrochemical impedance spectroscopy (EIS) is an application of biosensors that commonly used in biological sensing area. Performing impedance measurement will involve applying the voltage stimulus and acquiring the signal outcome. Thanks to the low-power consumption and simple circuit architecture, successive approximation register (SAR) ADC is often the major choice for impedance array sensing with moderate resolution and sampling rate. For mixed-signal designs like impedance array sensors, an on-chip processing unit is normally required. Designing a processing system using hardware description language (HDL) allows a fast-paced system design and verification while enhancing the processing unit function.

In this work, the design of an efficient SAR ADC for an impedance array sensor with the assistance of Verilog as well as the Image Signal Processing unit (ISP) for a CMOS Image Sensor is introduced.

Implementing a single-ended SAR ADC with bridged capacitor arrays based on a 0.18-um CMOS process, the SAR logic is designed and verified using Verilog coding and the capacitor array is built from MOM capacitors. The capacitor array layout is fully-customized for better matching performance. The size of a single ADC is 200 um x 344 um. This ADC samples at 1.67 MS/s and has 0.93 LSB DNL and 1.10 LSB INL. The power consumption of the ADC is about 270 uW. For the 657.6 kHz full-scale sinusoidal signal input, the ADC has an average ENOB of 11.15 bits with the absence of noise and 10.64 bits when noise is included. With the aid of the column ADC, the 2-stage quantizer scheme is used in the impedance array sensor to widen the dynamic range. The measurements ranges from 64 kΩ to 0.9 GΩ and the input signal ranges from 6 pA to 80 nA. The signal frequency can vary from 1 Hz to 100 kHz. The magnitude deviation is 1.49% with a 0.81 degrees phase variation and the power consumption is 478.8 uW per channel. The impedance sensing architecture enables a 10 x 10 array design on a 3 mm x 3 mm die.

Digital system design techniques apply to the design of an ISP for a CMOS Image Sensor. The ISP is able to control the chip memory, perform the auto exposure time tuning, achieve black level cancellation, signal outputting, carry out on-chip testing, take a serial input and output the register content, and control the pixel variable gain amplifier (VGA) and analog-to-digital converter (ADC) timing.