Low-latency and low-complexity list successive-cancellation decoding of polar codes
by Chen Ji
THESIS
2017
M.Phil. Electronic and Computer Engineering
x, 90 pages : illustrations ; 30 cm
Abstract
Polar codes have attracted a lot of research interests recently due to their provable capacity-achieving
performance. The decoders of polar codes include successive-cancellation decoder (SCD) and list
successive-cancellation decoder (LSCD). A SCD performs well when decoding long code lengths but has
large performance degradation in short-to-medium code length. LSCD is proposed to compensate the SCD
drawback. List size in an LSCD directly determines LSCD performance. LSCDs with a large list size
exceed that of Turbo codes and Low-Density Parity-Check codes. However, a large list size results in huge
computation complexity and increasing latency, and this limits the applicability of LSCDs in low-latency or
power-sensitive implementation. Therefore, a low latency and low complexity...[ Read more ]
Polar codes have attracted a lot of research interests recently due to their provable capacity-achieving
performance. The decoders of polar codes include successive-cancellation decoder (SCD) and list
successive-cancellation decoder (LSCD). A SCD performs well when decoding long code lengths but has
large performance degradation in short-to-medium code length. LSCD is proposed to compensate the SCD
drawback. List size in an LSCD directly determines LSCD performance. LSCDs with a large list size
exceed that of Turbo codes and Low-Density Parity-Check codes. However, a large list size results in huge
computation complexity and increasing latency, and this limits the applicability of LSCDs in low-latency or
power-sensitive implementation. Therefore, a low latency and low complexity LSCD design is proposed in
this thesis.
In a low-latency design, latency optimizations are carried out at the system and algorithmic levels. At
the system level, a selective expansion method is proposed such that some of the reliable bits are not
expanded at the LSCD for reducing the latency. At the algorithmic level, a double thresholding scheme is
proposed for a fast and good approximate-sort method for the list management operation in the LSCD to
reduce the decoding latency for a large list size. Experiments show that for a list size of 16, the
implementation achieves a decoding throughput of 465 Mbps by using UMC 90 nm CMOS technology
while the performance degradation when compared with the convention exact method is negligible.
In a low-complexity design, the property of the relative path metric (RPM) of each list candidate with
respect to that of the most-likely candidate is investigated. It is found that the correct candidate has a low
possibility of having a large value of RPM, and based on this property, a list pruning method and the
corresponding low-complexity LSCDs are proposed. From the simulation results, as compared to the
conventional LSCD, the proposed LSCDs have negligible performance loss while the computation
complexity is reduced by more than 80%. In addition, the proposed design is hardware-friendly and easily
adaptable to the existing LSCD hardware architectures.
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