Abstract
We have developed a methodology to convert polygon-based full-custom bulk CMOS cells to SOI/CMOS. This methodology is implemented using the Cadence Design Systems Virtuoso environment. We have demonstrated the methodology by converting the Orbit Scalable CMOSN standard cells. The results are quite good for small cells. However, for complex and highly optimized cell, this methodology may lead to a slight increase in the cell area. We have also demonstrated that this methodology can also be applied to further reduce the cell area if the SOIKMOS cells are redesigned to take advantage of the low-power and high-performance capability of SOI/CMOS. In this thesis we shall present the detail heuristics of the methodology.