THESIS
1996
viii, [83] leaves : ill. ; 30 cm
Abstract
A self-planarized Au metallization process by electrolytic plating has been developed for metal interconnections in the submicron range. Gold wires with high aspect ratio were fabricated in an embedded structure within the dielectric spacer. By etching of Au and oxidizing the surface of TiW in the field, the gold wires can be selectively formed within the dielectric. This process can provide desired properties of conductor structures for Si LSI applications....[
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A self-planarized Au metallization process by electrolytic plating has been developed for metal interconnections in the submicron range. Gold wires with high aspect ratio were fabricated in an embedded structure within the dielectric spacer. By etching of Au and oxidizing the surface of TiW in the field, the gold wires can be selectively formed within the dielectric. This process can provide desired properties of conductor structures for Si LSI applications.
As the number of device integration increases in electronic circuits, planarization become critical at both chip and package levels. Several planarization strategies were developed during metallization. In general they can be divided into two categories: one involves the deposition of dielectric and dielectric planarization; the other is metal planarization by filling metal in patterns, like selective tungsten CVD and electrolytic plating. Among the latter, copper and gold are the two metals which can be easily plated.
In fact, gold metallization by electrolytic plating has been widely used for microwave applications in either GaAs or silicon ICs. It is mainly due to its high conductivity hence low RC time constant. Its superior electromigration characteristic also makes it attractive for high-speed Si LSIs such as application in personal communications. While downsizing metal interconnection wires is necessary for high-speed LSIs, conventional gold metallization processing technology can no longer be suitable for forming interconnections with linewidth in the submicron range, due to the overetching and undercutting problems in wet-etching. Moreover, as reducing the metal linewidth, an increase in the metal thickness should be followed for good reliability. Therefore, metal wires with high thickness-to-width aspect ratio is required. Last but not the least, the high-aspect-ratio requirement demands good planarization process in order to gain high yield when forming second-layer metal interconnections. A process which can achieve metal wiring with high aspect ratio while keeping surface topology planarized is therefore deemed necessary.
A novel fabrication process is presented which allows us to form submicron gold interconnections with high aspect ratio. Electroplating in a selective way (selective electroplating) may be another important key technique to build a submicron interconnection particularly with a simple fabrication process. We developed the technique of selective electroplating, which enables self-planarized interconnections without any extra planarization process step prior to second-layer metallization. The new fabrication technology also offers potential low-cost productivity, because of no usage of ion-milling or polishing.
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