As the complexity of synchronous circuits grows, problems such as power consumption, thermal dissipation, and clock skew are emerging. Asynchronous design style offers solutions to all of the above problems and provides many other advantages. Other researchers also predicted that asynchronous circuits will be the mainstream in the future....[ Read more ]

As the complexity of synchronous circuits grows, problems such as power consumption, thermal dissipation, and clock skew are emerging. Asynchronous design style offers solutions to all of the above problems and provides many other advantages. Other researchers also predicted that asynchronous circuits will be the mainstream in the future.

The aim of this research is to develop a method for synthesizing asynchronous VLSI circuits from VLSI programs written in terms of concurrent processes. It is the most natural way to model system specification into concurrent processes. Since the inherent nature of digital circuit is concurrent, and also the nature of the computations to be implemented contains concurrence.

A.J. Martin's method to transform VLSI programs into asynchronous circuits consists of four steps: process decomposition, handshaking expansion, production rule expansion, and operator reduction. Shufling is an operation performed on the handshaking expansion to enable production rule expansion. We propose a new shuffling scheme- Symmetric Shufling Scheme (SSS). With SSS, the resulting circuits are smaller, the circuit networks are simpler, the compilation process is simpler. Pipelined SSS (PSSS) allows the circuit operation speed be traded for circuit size. Reentrant processes compiled by PSSS gives smaller circuit than by using channels. A silicon compiler based on A.J. Martin's compilation method enhanced with SSS and PSSS has been built. To evaluate the performance of SSS, an asynchronous microprocessor has been built. For comparison, the four-bit microprocessor was also implemented in a synchronous FPGA chip.