The semiconductor industry is constantly striving to improve operation efficiency by enhancing product competitiveness, reducing chip size, and increasing product yield and reliability. Design for Efficient Manufacturability (DFEM) is practised to achieve these aims which entails the prediction of the circuit behaviors and performances and the statistical variation of them prior to manufacturing. This implies accurate characterization of the processing technology with direct connection to the MOSFET model parameters used in the simulators, and the ability of relating the spread of the circuit parameters as a result of process variations....[ Read more ]

The semiconductor industry is constantly striving to improve operation efficiency by enhancing product competitiveness, reducing chip size, and increasing product yield and reliability. Design for Efficient Manufacturability (DFEM) is practised to achieve these aims which entails the prediction of the circuit behaviors and performances and the statistical variation of them prior to manufacturing. This implies accurate characterization of the processing technology with direct connection to the MOSFET model parameters used in the simulators, and the ability of relating the spread of the circuit parameters as a result of process variations.

The current methodology in use is a semi-open-loop approach. Model parameters and the variations of them are extracted from test runs, which are used to simulate circuit behaviors. When circuits are manufactured, their behaviors are measured, documented, and sold in different "performance bins". Yet, there is no study on the correlation between the circuit behaviors and characteristics of the real devices in the circuit. As such, the accuracy and the appropriateness of the simulation was never verified.

In this research, we investigate the design and characterization of compact testing structures that could be placed on the scribe-line(As the name implies, scribe-line is the narrow silicon estate between usable circuits along which the production wafer is sawed or "scribed". As such, it usually contains no circuit), yet contain an adequate set of devices for the characterization of both process and circuit level characterization, as well as their correlation. In order to be able to extract accurate and usable data, parasitic elements especially for the capacitance have to be minimized. Several schemes to reduce parasitic capacitance have been studied and their effectiveness investigated using numerical electromagnetic simulation and experiments.

Device parameters characterized by the scribeline structure are proved to be representative of the device behaviors and the conciseness is ideal for efficient statistical circuit performance analysis. A specially designed automation system is also developed for fast and accurate measurement and extraction of the device parameters. We have shown that an effective link between process and circuit level characterization can be established, that a more realistic circuit performance prediction and proactive control mechanism can be attained, and that a wider design window and reduced die sizes can be achieved.