The purpose of this research is to design and implement a low-power, high-speed, high-accuracy PAM (Pulse Amplitude Modulation) or QPSK (Quadra-ture Phase Shift Keying) modulator using a novel digital-to-analog current-division technique, which efficiently merges the FIR filtering operation and the DAC functions into the same circuitry....[ Read more ]

The purpose of this research is to design and implement a low-power, high-speed, high-accuracy PAM (Pulse Amplitude Modulation) or QPSK (Quadra-ture Phase Shift Keying) modulator using a novel digital-to-analog current-division technique, which efficiently merges the FIR filtering operation and the DAC functions into the same circuitry.

Design techniques and measured results of a prototype CMOS modulator for broadband PAM and QPSK data formats are presented. The circuit is based on a poly-phase implementation of a traditional all-digital architecture. Reduction in area and power is accomplished by using a digital-to-analog current-division square-root-cosine waveshaping converter. Digital data is applied at the input and a filtered analog waveform is produced at the output,without the need for a standard D/A converter at the back-end. The circuit has been fabricated in a O.8-μm CMOS process (MOSIS HPCMOS26G), occupies an area of 1.2-mm X 1.213-mm, and dissipates 30-mW from a single 5V supply. The maximum baud-rate of the modulator is l0-Mbaud at a sample-rate of 40-MHz. The 33-tap FIR waveshaping filter insures out-of-band ripples are suppressed by more than 32-dB. This modulator is applicable to broadband digital communication such as wireless telephony, wireless modems, digital video, and digital subscriber-line systems.