A Voltage-Control Oscillator(VCO) has been designed using 0.72um CMOS technology. The VCO will be integrated in a Clock Recovery Circuit(CRC) using the Data Transition Tracking Loop(DTTL) architecture. With the DTTL architecture, the clock recovery circuit is capable to handle the 1.25Gb/s Non-Return-to-Zero(NRZ) digital data, but the VCO center frequency is 625MHz. Brief overview and N4TLAB simulation of dynamics of the DTTL will be presented....[ Read more ]

A Voltage-Control Oscillator(VCO) has been designed using 0.72um CMOS technology. The VCO will be integrated in a Clock Recovery Circuit(CRC) using the Data Transition Tracking Loop(DTTL) architecture. With the DTTL architecture, the clock recovery circuit is capable to handle the 1.25Gb/s Non-Return-to-Zero(NRZ) digital data, but the VCO center frequency is 625MHz. Brief overview and N4TLAB simulation of dynamics of the DTTL will be presented.

Several ring VCO architectures have been studied. Investigation of VCO oscillation mechanism reveals that typical differential-pair VCO suffers the problem of variation of output amplitude with frequency. With the interpolating architecture, the problem could be alleviated.

In addition, interpolating VCO architecture has been extensively studied in terms of voltage-to-frequency characteristics, temperature-sensitivity and output jitter. By using a inverse-mobility current source, we could combat the ambient temperature change so that both center frequency and tuning range are kept unchanged. From simulation, the sensitivity of VCO center frequency achieves less than -lOOppm/℃ for the temperature range 0°C to 70°C.

Jitter analysis using the thermal noise model indicates the rms output jitter of the interpolating VCO has an l8% increase when compared with the purely differential pair counterparts. Monte Carlo simulation shows rms VCO jitter to be 400fs with power consumption of 65mW.